JPH07101392B2 - Tracer - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a tracer having means for writing information of hardware of an information processing device to a RAM according to a preset condition, and sometimes reading of the tracer. It is related to the method.

[Conventional technology]

Conventionally, this type of tracer has a tracer address updating means from the tracer reading means and a parallel read path,
According to the instruction from the tracer reading means, the data of one address (one word at a time) is read in parallel paths.

[Problems to be Solved by the Invention]

In the above-mentioned conventional tracer, since the parallel path is used, when the tracer reading means controls a plurality of information processing devices, the parallel paths are required for the number of information processing devices, and the amount of hardware is pinned. There was a problem of increase.

[Means for Solving the Problems]

The tracer of the present invention is a tracer having information writing means for writing information of hardware of an information processing device according to a preset condition in RAM, and when a predetermined condition occurs, information of Writing stop means for stopping writing, and writing stop notifying means for notifying the tracer data reading means that writing of information to the RAM has stopped,
In response to the notification from the write stop notifying means, the first read instruction generating means for generating the read instruction in the tracer data reading means, and the read instruction from the tracer data reading means, are stored in the address register at that time. Trace data setting means for setting one word of trace data in the RAM designated by the RAM address in the shift register, and the RAM address stored in the address register when the trace data is set in the shift register by the trace data setting means And RAM address updating means for updating the tracer data reading means and shift-out for shifting out the contents of the shift register to the tracer data reading means by the shift clock which starts to be output together with the read instruction generated by the first read instruction generating means Means and 1 word Second read instruction generating means for generating a read instruction in the tracer data reading means each time a shift clock for the trace data is output, and writing to the RAM after shifting out all the data in the RAM to the tracer data reading means. And a writing restarting means for restarting the writing.

[Action]

In the present invention, the tracer data is read by the shift path, the tracer data is set in the shift register for each word, and the tracer data is continuously read.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of the tracer unit according to the embodiment of the present invention.

In the figure, 1 is a trace RAM, 2 is a selector, and 3 is R.
AM1 address register, 4 is an address update adder,
Reference numeral 5 is a shift register that holds read data from the RAM 1, 12 is a trace mode register, and 13 is a tracer write control circuit. Note that 100,101 ... 107,110,113,11
4, 116, 117 and 118 indicate signal lines, and 108 indicates a path. Further, the CS1 address and the CS2 address are a control memory (1) address and a control memory (2) address, respectively, and the IC is an instruction counter.

FIG. 2 is a block diagram of the tracer data reading means of the embodiment of the present invention.

In FIG. 2, the same reference numerals as those in FIG. 1 indicate corresponding parts, 8 is a counter, 9 is a tracer shift mode flip-flop, 10 is an AND gate, 11 is a shift register, 14 is a tracer read control circuit, 15 is a falling differentiation circuit,
Reference numeral 16 is a rising / falling differentiation circuit, and 17 is an OR gate.
Note that 105, 106, 112, and 119 denote signal lines.

The trace RAM 1, the selector 2, the trace mode register 12, and the tracer write control circuit 13 constitute an information writing means for writing the information of the hardware of the information processing device in the RAM according to a preset condition. ,Also,
The trace mode register 12 and the tracer write control circuit 13 constitute write stop means for stopping the write when a predetermined condition occurs, and the tracer write control circuit 13 and the signal line 11
Reference numeral 6 constitutes a write stop notifying means for notifying the tracer data reading means of the stop.

The tracer read control circuit 14 constitutes a first read instruction generating means for generating a read instruction in response to the notification from the write stop means, and the OR gate 17, the signal line 105 and the signal line 119.
Is stored in the address register 3 in response to a read instruction from the tracer data reading means.
The trace data setting means for setting the 1-word trace data in the RAM 1 designated by the address in the shift register 5 is constituted, and the address updating adder 4 is set in the address register 3 when the trace data is set in the shift register 5. The RAM address updating means for updating the stored RAM address is configured. The shift register 5, the AND gate 10, the shift register 11, the signal line 106 and the shift path 108 constitute a shift-out means for shifting out the contents of the shift register 5 to the tracer data reading means by the shift clock from the tracer data reading means. ing. Further, the counter 8 and the rising / falling differentiation circuit 16 constitute a second read instruction generating means for generating a read instruction each time a shift clock for one word of trace data is output, and the counter 8 and the tracer shift mode. The flip-flop 9 and the falling differentiating circuit 15 constitute a write resuming means for resuming writing to the RAM1 after shifting out all the data to the RAM1 to the tracer data reading means.

Next, the operation of the embodiment shown in FIGS. 1 and 2 will be described.

First, from the service processor, trace mode register
Set the trace mode to 12 in advance at the time of initial setting. Then, for example, in the case of the mode in which the CS1 address is clock-traced every time the data designated by the trace mode register 12 is selected, the selector 2 selects the CS1 address and the signal is transmitted through the signal line 107 from the write control circuit 13. Write to each clock RAM1 by output instruction. Here, when the stop condition, for example, the stop condition is satisfied due to the occurrence of an error, the signal passing through the signal line 114 becomes valid, and the write control circuit 13 stops the write. Then, this stop is notified to the tracer data reading means shown in FIG. 2 by a signal passing through the signal line 116, and by the read instruction signal from the read control circuit 14 passing through the signal line 119, the tracer shift mode flip-flop. 9 is set and ANDed with the clock signal by the AND gate 10 to start sending the shift clock signal to the tracer section through the signal line 106.

At the same time, a read instruction signal passing through the signal line 119 is sent to the trace unit through the OR gate 17 and the signal line 105. The trace unit receives the read instruction signal and shifts the 1-word trace data in RAM1 designated by the RAM address at that time (RAM address when writing is stopped) stored in the address register 3. At the same time as setting in the register 5, the contents of the address register 3 are incremented by 1 by the address updating adder 4. The shift clock signal is then continuously output through the signal line 106, and is shifted out from the shift register 5 to the shift register 11 through the shift path 108. When 16 bits of data for one word are output, that is, when a shift clock for one word of trace data is output, the output in the middle of the counter 8 is changed to a rising / falling differentiation circuit.
A read instruction signal is generated by differentiating at 16 and this read instruction signal is sent to the trace unit via the OR gate 17. The trace unit receives the read instruction signal sent and stores the RA stored at that time in the address register 3.
RAM1 designated by M address (+1 incremented RAM address)
The trace data of one word is set in the shift register 5 and at the same time, the content of the address register 3 is incremented by 1 by the address updating adder 4.

The counter 8 counts the number of shift clocks, and the RAM1
When all the data in it have been shifted out to the shift register 11, the tracer shift mode flip-flop 9 is reset. As a result, the transmission of the shift clock signal is stopped, and at the same time, the trailing edge differentiation circuit 15 outputs a pulse to the signal line 117 to instruct the tracer writing control circuit 13 to start writing.

Then, the tracer data reading means edits the shifted out data and stores the edited data in a disk to prepare for a reading instruction from the service processor.

In this embodiment, one bit of dummy data is read into the shift register 11 when a read instruction for each word is issued, but this dummy bit is removed during editing.

〔The invention's effect〕

As described above, the present invention has means for reading the tracer data by the shift path and means for setting the tracer data for each word in the shift register and continuously reading the tracer data. Using one shift path, there is an effect that it can be read at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram of the tracer section of the embodiment of the present invention, and FIG. 2 is a block diagram of the tracer data reading means of the embodiment of the present invention. 1 ... Trace RAM, 2 ... Selector, 3 ... Address register, 4 ... Address update adder, 5 ... Shift register, 8 ... Counter, 9 ... Tracer Shift mode flip-flop, 10 ... … And gate, 11 …… Shift register, 12 …… Trace mode register, 13 ……
Tracer write control circuit, 14 ... Tracer read control circuit, 15 ... Falling differentiation circuit, 16 ... Rising / falling differentiation circuit, 17 ... OR gate.

Claims (1)

[Claims] 1. A RAM for information of hardware of an information processing device
A tracer having information writing means for writing in accordance with a preset condition, write stop means for stopping writing information in the RAM when a predetermined condition occurs, and writing information in the RAM Write stop notifying means for notifying the tracer data reading means that the reading has stopped, and first read instruction generating means for generating a read instruction in the tracer data reading means in response to the notification from the write stop notifying means. Trace data setting means for setting, in a shift register, one word of trace data in the RAM which is stored in an address register and is designated by the RAM address at that time, in response to a read instruction from the tracer data reading means, When setting the trace data to the shift register by the data setting means, RAM address updating means for updating the stored RAM address, and a shift clock that starts to be output together with the read instruction generated by the first read instruction generating means from the tracer data reading means, and the contents of the shift register are traced by the tracer. Shift-out means for shifting out to the data reading means; second read-instruction generating means for generating a read instruction in the tracer-data reading means each time the shift clock for one word of trace data is output; And a write resuming means for resuming writing to the RAM after all the data in the RAM is shifted out to the data reading means.