JPH01150945A - Tracer - Google Patents

Abstract

PURPOSE:To execute the reading of tracer data at a high speed with using one shift pass by equipping a means to read the tracer data with a shift pulse and a means to set the tracer data to a shift register and to successively read the tracer data. CONSTITUTION:A tracer shift mode flip-flop 11 is set by a shift starting signal from a tracer stop control circuit 15 through a signal line 105 and the AND of the output of this tracer shift mode flip-flop 11 and a clock signal is executed in an AND gate 12. Then, a shift clock signal is sent through a signal line 106 to a tracer part. Next, an OR is executed in an OR gate 7 and the data of a RAM1 for trace are set to a shift register 5. Then, the contents of an address register 3 are caused to be +1 by an adder 4 for address renewal. After that, a shift clock from the signal line 106 is successively outputted and read from the shift register 5 through a pass 112 to a shift register 12 at the high speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a tracer connected to an information processing device.
In particular, the present invention relates to a method for reading a tracer having means for writing information on the hardware of an information processing device into a RAM according to preset conditions.

[Conventional technology]

Conventionally, this type of tracer has a tracer address update means from a tracer readout means and a parallel readout path;
Data of one address (one word at a time) was read in parallel paths according to instructions from the tracer reading means.

[Problem that the invention seeks to solve]

In the conventional tracing described above, parallel paths are used, so when the tracer reading means controls multiple information processing devices, parallel paths are required for the number of information processing devices, resulting in a pin-neck and a reduction in hardware costs. There was a problem that the amount increased.

[Means for solving problems]

The tracer of the present invention has means for writing hardware information of an information processing device into a RAM according to preset conditions, and includes means for stopping writing when a predetermined condition occurs; A means for notifying the tracer data reading means that the tracer has been stopped, a shift pulse data holding data read from the tracer, and a trace specified by the RAM address when the shift is stopped in response to a shift start instruction from the tracer data reading means. means for setting data in the shift register; means for updating the RAM address when data is set in the shift register by the means; and tracer data reading means for reading the contents of the shift register using a shift clock from the tracer data reading means. means for setting the next trace data in the shift register when a shift clock for one word of trace data is issued; and means for restarting writing to the tracer after reading all the words of the tracer. It is equipped with the means to do so.

[Effect]

In the present invention, tracer data is read by a shift pulse, tracer data is set in a shift register word by word, and the tracer data is read out continuously.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram of a tracer section showing an embodiment of the present invention.

In the figure, 1 is a trace RAM, 2 is a selector, and 3 is a trace RAM.
is an address register for RAM1, 4 is an address update adder (+1 circuit), 5 is a shift register that holds read data from the tracer, 6 is a counter, and 7 is an overflow 109 from this counter 6 and a shift from the signal line 105. An OR gate receives a start signal, 8 is a mode register, and 9 is a tracer write control circuit.

100 in this Figure 1 is the C81 address,
101 is the C82 address, 102 is the signal from the instruction counter (IC), 103 is the memory interface signal, and 104 is the trace RA from selector 2.
Signal to M1, 106 is signal line, 107 is signal, 10
8 is a signal line, 110 is from adder 4 to address register 3
113 is a signal from the mode register 8 to the selector 2, 114 is a signal indicating a stop condition, 116 is a tracer stop signal, and 117 and 118 are signal lines.

FIG. 2 is a block diagram showing an embodiment of tracer data reading means used in the present invention.

In the figure, 10 is a counter, 11 is a tracer shift mode flip-flop, 12 is an AND gate which receives the output of this tracer shift mode flip-flop 11 and a clock, 13 is a shift register, 14 is a tracer stop control circuit, and 15 is a stand-up The down differential circuit constitutes tracer data reading means.

Note that in FIG. 2, the same reference numerals as in FIG. 1 indicate the monk part, and 112 is a pass.

The tracer write control circuit 9 constitutes means for writing hardware information of the information processing device into the RAM according to preset conditions, and the mode register 8 and the tracer write control circuit 9 constitute means for writing hardware information of the information processing device into the RAM according to preset conditions. The tracer write control circuit 9 and the tracer stop signal 116 constitute means for notifying the tracer data reading means that the writing has been stopped by the means for stopping the writing. ing.

On the other hand, the OR gate T serves as a means for setting the trace data specified by the RAM address in the shift register 5 when stopped by a shift start instruction from the tracer data reading means, and the adder 4 provides a means for setting the trace data in the shift register 5. The shift register 5, the tracer shift mode flip-flop 11, the AND gate 12, the shift register 13, and the signal lines 106 and 108 are connected to the shift register 5, the tracer shift mode flip-flop 11, the AND gate 12, the shift register 13, and the signal lines 106 and 108. It constitutes means for shifting out the contents to the tracer data reading means. Further, the shift register 5, the counter 6, and the OR gate 7 constitute means for setting the next trace data in the shift register 5 when a shift clock for one word of trace data is issued.
Counter 10, tracer shift mode flip-flop 11 and falling differentiator circuit 15 constitute means for resuming writing to the tracer after reading all words of the tracer.

Next, the operation of the embodiment shown in FIGS. 1 and 2 will be explained.

The trace mode is previously set in the mode selector 8 from the mass/service processor at the time of initial setting. For example, the data specified by this mode selector 8 is
, in the mode in which address 100 is traced every tarot trace, C8t address 100 is selected by selector 2, and written into RAM 1 for every tarot trace in response to an output instruction from tracer write control circuit 9 through signal 107. When the stop condition, for example, the stop condition is satisfied due to the occurrence of an error, the signal 114 becomes valid, and the tracer write control circuit 9 informs the tracer data reading means of the configuration shown in FIG. signal 11
6, the tracer stop control circuit 14 sets the shift start signal Kjb through the signal line 105 to the tracer shift mode flip-flop 11, and the output of the tracer shift mode flip-flop 11 and the clock signal are ANDed by the AND gate 12. Then, the shift clock signal is sent to the tracer section shown in FIG. 1 through the signal line 106.

Next, when a shift start signal is sent through the signal line 105, it is ORed by an OR gate T and the data of the trace RAM 1 is set in the shift register 5.

At the same time, the contents of the address register 3 are incremented by 1 by the address update adder 4. The shift clock from signal line 106 is then continuously output and read out from shift register 5 to shift register 13 via path 112. When 16 bits of data corresponding to one word are output, an overflow 109 is detected by the counter 6, the address register 3 is incremented by 1, and the output of the trace RAM 1 is set in the shift register 5.

Counter 10 counts the number of shift clocks,
Once all data of the tracer has been read to the shift register 13, the tracer shift out is stopped by resetting the tracer shift mode flip 70 knob 11, and the tracer shift mode flip-flop 1 is reset.
The falling differential circuit 15 outputs a υ pulse to the signal line 117 to instruct the tracer write control circuit 9 to start writing.

The read control means then edits the contents of the shift register 13 and stores it in an auxiliary storage device, for example, a disk device, in preparation for a read instruction from the service processor.

In the above reading sequence, 1-bit dummy data is read into the shift register 13 for each word, but this dummy data is also removed during editing.

〔Effect of the invention〕

As explained above, the present invention has means for reading tracer data using a shift pulse and means for setting tracer data in a shift register word by word and reading out the tracer data continuously. This has the advantage that it can be read out at high speed using one shift pass.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a tracer section showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an embodiment of tracer data reading means used in the present invention. 11111@・RAM for tracing, 2... life selector, 3φ... address register, 4@・skewer/adder, 5
・・・Shift register, 6・-counter, 7・・
...OR gate, 8...Mode register, 9...
・Tracer write control circuit, 10...Counter, 1
1--Fist trace shift mode flip-flop, 1
2...AND gate, 13...Adjustment shift register, 14...Tracer stop control circuit, 15...Fall differential circuit. Patent applicant: NEC Corporation

Claims (1)

[Claims] A tracer having a means for writing hardware information of an information processing device into a RAM according to preset conditions, and a means for stopping the writing when a predetermined condition occurs, and a means for stopping the writing by this means. means for notifying a tracer data reading means of this, a shift register for holding read data from the tracer, and a shift register for storing the tracer data indicated by the RAM address when the shift is stopped by the shift start instruction from the tracer data reading means means for setting in the shift register; means for updating the RAM address when setting in the shift register by the means; and shifting out the contents of the shift register to the tracer data reading means using a shift clock from the tracer data reading means. means for setting the next trace data in the shift register when a shift clock for one word of tracer data is issued; and means for restarting writing to the tracer after reading all the words of the tracer. A tracer characterized by comprising: