SU1246140A1 - Storage with program correction - Google Patents

Abstract

The invention relates to storage devices, in particular to storage devices implemented on an LSI and controlled computing devices. The goal of the inventions is not the speed of the mouth-. roystva The device contains a block: a fixed memory, a block of semi-permanent memory, switches, a register of numbers, AND elements, blocks of AND elements, pulse shapers, an address register, inputs and outputs of the device. The device operates in two modes: in the operating mode of automatic program correction during initial debugging of the system or retooling of the system for new tasks; in the manual correction mode of the numbers recorded in the semi-permanent memory. This includes the mode of initial inputting of corrected numbers into a block of semi-permanent memory. 3 il. with (L

Description

one

The invention relates to storage devices, in particular to storage devices implemented on an LSI and controlled computing devices (computers).

The purpose of the invention is to increase the speed of the device.

Figure 1 shows a block diagram of a storage device with a program correction; FIG. 2 is a time diagram of the device operation in the program automatic correction mode; FIG. 3 shows a temporary diagram of the operation of the device in the mode of manual program correction.

The device contains the first control input 1, block 2 of permanent memory, register 3 of the initial state code, block 4 of semi-permanent memory, first 5 switch, re

rist 6 numbers, clock 7 input, second control input 8, address input 9, first 10, second 11, third 12 outputs, first 13, second 14 elements AND, first 15, second 16 pulse drivers, first 17, second 18 blocks of elements And, the second switch 19, the address register 20.

The device works in two modes:

in the operating mode of automatic program correction during the initial debugging of the system or the changeover of the system to new tasks,

in the mode of manual correction of the numbers recorded in the 4 semi-permanent memory block. This includes the mode of initial numbers to be corrected in the water in block 4 of a semi-permanent memory.

According to the initial start signal in each of the modes, the first and second drivers are reset to the zero state, i.e. The device is prepared for operation.

The operation of the device in the automatic correction mode is specified by the scoring signal received at control input 1 (Fig. 3a |, which allows the passage of clock pulses (input 1) through the first element And 13 (fig. 36} to the input of the first 15 driver). 152 generator, a read address transfer permission signal is generated, which enables the passage of the address code t from the bus 9 through the first

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thirty

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block 17 elements And (fig.Zv) on the first inputs of the switch 19. At the same time, but the signal Read opens the switch 19 on the first inputs, i.e.

5 permits the output of the address code to the address inputs of the blocks of a constant 2 and semi-permanent 4 memory. At the output of the 15. generator, a memory readout signal (FIG. 3) is generated, which reads information from blocks 2 and 4 to the previously set address. Information from blocks 2 and 4 is fed to the inputs of block 5.

In block 4 of semi-permanent memory

15, there is an additional data bit (second output of block 4) indicating the presence of a correction at each address.

If the information is corrected,

20, the unit level at the second output of block 4 permits the passage through the commentator 5 of information from block 4. If the information in block 2 is correct, the second output of block 4 contains a logic zero level and through the switch 5 passes information read from block 2.

The signals on the first control and information outputs of the storage device with program correction are fed to the output device for further processing.

After the program is executed, the computing device removes the signal. Reading and the memory with program correction in the automatic correction mode is terminated.

In the manual correction mode, the numbers recorded in block 4 of the semi-permanent memory, or the initial input of the correct numbers, the address of the record is set on register 20, and the information on register 3 of the code of the original bos; Signal Record arriving at control input 8 (FIG. 4a). | allows clock pulses to pass through the second 4 element I to the input of the second 16 driver, at the third 16 output of which a number register control signal is formed (Fig. 4c), according to which information from register 3 of the initial state code is written to register 6. Thereafter, 16, (FIG. 4d) of the second driver, a signal for breaking up the transmission of the recording address is formed, permitting passage 31

the address code from register 20 through the second block 19 elements - And to the second inputs of the switch 19, open through the second inputs, and further to the address inputs of blocks 2 and 4; At the output 16 of the driver, a signal is written Record memory (fig.4d) information is recorded in block 4 of semi-permanent memory. Signal Record of memory is the second control output of the memory device, is fed to the control input of the computing device, is fed to the control input of the computing device. After the termination of this signal, the computing device can generate the next signal Record, which will be recorded at a different address.

Claims (1)

. Formula of gain A memory device with program correction, containing a constant memory block, a number register whose information inputs are connected to the outputs of the initial state code register, and the outputs to information inputs of a semi-permanent memory block, one output of which is connected to the first input the first switch, characterized by the fact that, in order to increase the speed of the device, it contains the second switch, the address register, the first and second blocks of the And elements, the first and second pulse shapers, the first and second And elements, the first inputs of which are the clock input of the device, the first and second control inputs of which are the second inputs of the e404 The control input of the second switch is connected to the first control input of the device, the output of the first element I is connected to the input of the first pulse shaper, the first output of which is connected to the control input of the permanent memory unit, the first control input of the semi-permanent memory block and is the first output of the device, the second output of the first pulse shaper is connected to the first input of the first block of elements AND, the second input of which is the address input of the device, the output of the first block of elements of AND with the second information input of the second switch, the second information input of which is connected to the output of the second block of I elements, the output of the second switch is connected to the address inputs of blocks of permanent and semi-permanent memory, the second input of the second block of I elements is connected to the output of the address register, the output of the second element I is connected to the input of the second pulse generator, the second output of which is connected to the first input of the second block of elements I, the first output of the second pulse driver is connected to the second control it is the input of the semi-permanent memory unit and is the second output of the device, the third output of the second pulse shaper is connected to the control of the number register input, another output of the semi-permanent memory unit is connected to the second input of the first switch, the third input of which is connected to the output a fixed memory unit, the output of the first switch is the third output of the device. but. five. v-g rZDC DCZTZDC.a Fmg.2 , ™ "P1 .J FIG.