JPS61173339A - First-in first-out buffer control device - Google Patents

Abstract

PURPOSE:To make an input and output permitting signal continuous, and to execute the high speed processing by remaining a preliminary buffer for one step or preliminary data for one step and non-permitting the input and non- permitting the output before the storing condition of the data to a buffer goes to be full or empty. CONSTITUTION:At a first-in first-out buffer circuit, a data shift register DSR of (n) steps having data latch circuits B1-Bnm and an indication shift register LSR having data control circuits A1-An are provided. When data control information of a circuit A2 is off, the data control information of the circuit A3 is latched to FF1, and an input permitting signal IR2 is outputted by AND with the output of FF1 and the control information of the circuit 2 at a gate circuit 4. An output permitting signal OR2 is generated in accordance with the control information of circuits An-1 and An in the same way by an FF2, inverters 7 and 8 and a gate circuit 5, a signal OR2 is turned off by the logical output of the output of the circuit An and the output of an FF3, and the input and output permitting signals are made continuous.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a first-in, first-out buffer control device for controlling a first-in, first-out buffer for temporarily storing transfer data in a data processing device.

[Conventional technology]

Conventionally, this type of first-in, first-out (hereinafter referred to as FIFO) buffer control device has an index shift register ■SR and m consisting of a 1-bit×n stage data management circuit A, , A2 . . . An as shown in FIG. Pintos 0
stage data launch circuit Bll.

B21...BnlTl and a data shift register DSR. The indication shift register ISR is the data shift register DSR. The data to be latched D,...Dm is the data register DSR.
The input permission signal IRI, which indicates that data can be input to the data shift register DSR, is used to manage information on whether data has arrived at the data management circuit A of the first stage of the indication shift register ISR. Management information ■1 is inverted and used, data shift register DS
The output permission signal ORI indicating that data can be taken from R is data management information (2) of the data management circuit An at the final stage of the indication shift register ISR. are using.

FIG. 4(a) shows a time chart for data input operation. The data management circuit A is controlled by the data input control signal SI input to the index shift register ISR.
1, strobe ST to each data latch circuit B11...Blm of the first stage of data shift register DSR.
B is created and the data is moved, and the data management information 1.B of the data management circuit A1 is created. becomes ON. When the data management information I is turned ON, the second stage data latch circuit B2+...8 of the data shift register DSR
If 2m is empty, a strobe signal 5TB2 is generated in the data management circuit A2 to each of the second-stage data latch circuits B21...82m, and the strobe signal 5TB2 is transmitted from the first-stage data latch circuit to the second-stage data latch circuit. At the same time as data movement is performed, data management information (1) is turned off and data management information (2) of the second stage data management circuit A2 is turned on. Such operations are performed sequentially in subsequent stages. Input permission signal IR
I uses the inverted information of the data management information 1. Therefore, the data management information 1.1 is used as shown in FIG. 4(a).
Each time the input permission signal IRI is turned ON, the input permission signal IRI is turned OFF, disabling input to the data shift register DSR.

FIG. 4(b) shows a time chart of the output operation. In response to the supply of the data output control signal SO to the indication shift register ISR, the data management circuit An turns on the strobe signal 5TBn to the final stage data latch circuit. Bnl...Br1r11 to send out the data stored in these circuits. As a result, the data management information In of the data management circuit An is turned OFF, and as a result, the data management circuit An-1 turns off the strobe signal S.
Turning on T B n-+, the above operations are sequentially performed in the previous stage. Since the output permission signal ORI uses the data management information In, as shown in FIG. 4(b), each time the data management information In turns OFF, the output permission signal ORI also turns OFF, and the output from the data shift register DSR. is not permitted.

[Problem that the invention seeks to solve]

As described above, in the conventional FIFO buffer control device, the use of the FIFO buffer is restricted by temporarily disabling input for each data input operation and temporarily disabling output for each data output operation, and restricting the use of the FIFO buffer when the next input/output operation is performed. There is a drawback that the FIFO buffer cannot be used at high speed because it must be waited for each time it is used.

[Means for solving problems]

SUMMARY OF THE INVENTION An object of the present invention is to provide a FIFO buffer control device which can solve the above-mentioned conventional drawbacks and can perform high-speed processing by continuously outputting an input permission signal and an output permission signal.

The present invention provides a first-in, first-out buffer control device that controls a data input permission signal that allows data input and a data output permission signal that allows data output to a first-in, first-out buffer consisting of an n-stage buffer (n is a natural number of 3 or more). At least the second stage, the third stage, the (n-2)th stage, the (
n-1) data management information generation means for generating data management information indicating whether or not data is stored in each of the buffers in the stage and nth stage, and data management in the buffer in the second stage; The data input permission signal is generated in response to the information and the data management information of the third stage buffer, and the data is stored in the second stage buffer and the third stage buffer. data input permission signal generating means for stopping generation of the data input permission signal only when the data input permission signal is present; data management information of the (n-2)th stage buffer; and data of the (n-1)th stage buffer; In response to the supply of management information, the data output permission signal is generated, and the data output permission signal is generated, and
) data output permission signal generating means that stops generating the data output permission signal only when no data is stored in the nth stage buffer; and means for canceling the stoppage of generation of the data output permission signal based on the data management information.

〔Example〕

Next, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The FIFO buffer control device shown in FIG. It consists of data shift register DSR
and the indication shift register ISR are the same as the conventional circuit shown in FIG. 3, and the structure thereof has been described above, so a description thereof will be omitted. Flip-flow knob 1 transfers data management information I3 of data management circuit A3 to data management circuit A.
The data management information I2 of 2 is latched in the OFF state, and the gate circuit 4 performs a NAND between the output information of the flip-flop 1 and the data management information I2 to generate an input permission signal IR2.
is being created. Therefore, only when the data management information I2 and 13 are both ON (this indicates that the FIFO buffer is full except for one stage), the input permission signal IR2 turns OFF and input is not permitted. flip flop 2
is the value inverted by the inverter 7 of the data management information In-2 of the data management circuit An-2.
-1 data management information In-I is latched in the ON state,
In the gate circuit 5, the output information of the flip-flop 2 and the inverted value of the data management information In-1 are NANDed to generate an output permission signal OR2. Therefore data management information■. Only when both -2 and In-1 are OFF (
This indicates that the FIFO buffer is empty with one stage of spare space remaining), and the output permission signal OR2 is turned OFF, disabling output. When the flip-flop 3 is turned ON by the instruction signal from the lower-level device and it is recognized that the final data is to be retrieved, the output permission signal OR2 is turned ON by the data management information In.

FIG. 2(a) shows a time chart of input operation in the embodiment of FIG. 1, and FIG. 2(b) shows a time chart of output operation of the embodiment of FIG. The input operation and output operation will be explained in detail with reference to FIGS. 1 and 2.

FIG. 2(a) shows that at time to, the data latch circuits in the first, second, and third stages of the FIFO buffer are empty, and the data latch circuits in the fourth and subsequent stages are filled with data. state (representatively, the fourth stage data management circuit A4
3 shows a time chart of an input operation from the data management information I4 (which shows that the data management information I4 is in the ON state).

In the state of time to, the output of flip-flop 1 is logic “
0" (hereinafter, ON state is indicated as logic "1" and OFF state is indicated as logic "O"), and input permission signal IR2 is logic".
Here, the data input control signal SI from the host device arrives at the indication shift register ISR at time t1, and the input data is transferred from the first stage data latch circuit to the second stage data latch circuit in the data shift register DSR. The data management information I3 of the third stage data management circuit A3 becomes a logic "" at time t2. 1", and in response, the input of flip-flop 1 also becomes logic "1". Since at least the output of flip-flop 1 is logic "0" until time t2, even if the data management circuit in the second stage Data management information of A2 ■Even if 2 becomes logic “1”, input permission signal IR
2 is maintained at logic "1", and the input permission signal IR2 changes to logic "O" (second
From time t2 onwards, the logic "1" of the input permission signal IR2 is maintained due to the logic "0" of the data management information (2). Next, at time t3, the data input control signal S is supplied from the host device to the indication shift register ISR, and the FI
When the input data is moved and stored in the FO buffer to the first stage data latch circuit and the second stage data latch circuit, the data management information I2 becomes logic "1" at time t4.
”. Since all the data is latched in the data latch circuits from the third stage onward, the above operation will cause the FIFO
The buffer, leaving only the first stage data latch circuit, becomes full of data and does not accept any more data. That is, at time t4, in response to the change of data management information 2 to logic "1", input permission signal IR2 is set to logic "0" to prohibit input. The reason why the flip-flop 1 eliminates the influence of the change in the data management information I3 in the logic "1" state of the data management information II is the response of the data management information II in response to the rise of the strobe signal 5TB3. This is to prevent malfunctions when both data management information 2 and I3 become logic "1" due to the difference in response time from the response of data management information I3. It is possible to increase the speed.

FIG. 2(b) shows that at time 1 (, for convenience, the same symbols as in FIG. 2(a) are used for time display), the (n-2)th yIt and (n-1)th ) stage data latch circuit stores data, and
The data latch circuits before the n-3)th stage are in an empty state (representatively, the data management information I n-3 of the data management circuit An-3 of the (n-3)th stage is logic "0". In this state, the output of the flip-flop 2 is at logic “0”.
'', therefore, the output permission signal OR2 is logic "1". Here, the data output control signal SO arrives from the lower device to the indication shift register ISR at time t1, and the data latch circuit of the nth stage At the same time, the data of the (n-1)th stage data latch circuit is shifted to the nth stage data latch circuit, and the data of the (n-1)th stage data latch circuit is outputted.
-2) The data of the data latch circuit of the (fl-1)th stage is
)-th stage data latch circuit. At time t2, the data management information I n of the data management circuit An-2
-2 becomes a logic "0" and in response, the output of the flip-flop 2 becomes a logic "1". Since at least the output of flip-flop 2 is logic "0" until time t2,
Even if the data management information In-1 of the (n-1)th stage data latch circuit becomes logic "0", the output permission signal O
The logic "1" of R2 is maintained, and the output permission signal OR2 becomes logic "0" every time the output is performed (as shown in FIG. 2(b)), as in the conventional device.
(indicated by a dotted line) is prevented. After time t2, the logic "1" of the data management information I n-1 maintains the logic "1" of the output permission signal OR2.Then, the logic "1" of the output permission signal OR2 is maintained.
3, the data output control signal SO is supplied from the lower device, the data of the n-th stage data launch circuit is output, and the data of the (n-1)th stage data latch circuit becomes the data of the n-th stage. When shifted to the latch circuit, the data management information In-1 of the data management circuit An-1 becomes logic "O" at time t4, and all data latch circuits before the (n-2) first stage store data. Therefore, with the above operation, the FIFO buffer becomes empty except for the nth stage data latch circuit, and the logic of data management information tn-t is changed at time t4 so that no more data is sent out. In response to the change to "0", the output permission signal OR2 is set to logic "O" and output is prohibited. Flip-flop 2 sets data management information I n-1 to logic “0”
It is the strobe signal S T B n- that eliminates the influence of the change in the data management information I n-2 in the state of
Due to the difference in response time between the response of data management information I n-1 and the response of data management information I n-2 in response to the rising edge of data management information I n-2, both data management information I n-1 and I n-2 Φ is used to prevent malfunction when the logic becomes "0", and by doing so, it is possible to further increase the speed.

When data is stored only in the n-th stage data latch circuit, if this data is the final data and needs to be taken out, the flip-flop 3 is turned ON by an instruction signal from the lower device, and an output permission signal is sent. OR2 is logic “1”
” to enable data output.

As described above, according to this embodiment, it is possible to prevent temporary inhibition of input every time input is performed and temporary prohibition of output every time output unlike conventional devices, so high-speed data input, Capable of high-speed output.

Although one embodiment of the present invention has been described above, the present invention is not limited to this embodiment, and it goes without saying that various modifications and changes can be made within the scope of the present invention.

(Effects of the Invention) According to the present invention, a spare buffer for one stage is left and input is not permitted before the storage state of data in the FIFO buffer 1 becomes full, and input is not permitted before the storage state of FIFO buffer 1 becomes empty. The input permission signal and the output permission signal are continuously output by leaving the preliminary data for the stages and disabling the output. becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart of input and output operations of the FIFO buffer control device shown in FIG. 1, and FIG. 3 is a block diagram of a conventional FIFO buffer control device. , FIG. 4 is a time chart of the input operation and output operation of the FIFO buffer control device of FIG. 3. 1.2.3...Flip-flop 4.5.6...Gate circuit 7.8...Inverter Bll~13nm...Data latch circuit A, #An
... Data management circuit ISR ... Indication shift register DSR ... Data shift register SI ...
・Data input control signal SO...Data output control signal I, xin...Data management information IR1, IR2・Input permission signal ORI, OR2・Output permission signal

Claims (1)

[Claims] (1) In a first-in, first-out buffer control device that controls a data input permission signal that allows data input to a first-in, first-out buffer that includes n stages (n is a natural number of 3 or more) and a data output permission signal that allows data output,
At least the second stage, the third stage, the (n-2)th stage, the (n-th stage)
1) data management information generation means for generating data management information indicating whether or not data is stored in each of the buffers in the second stage and the nth stage; and data management information for the second stage buffer; When the data input permission signal is generated in response to the data management information of the third stage buffer, and data is stored in the second stage buffer and the third stage buffer. data input permission signal generation means for stopping generation of the data input permission signal; data management information for the (n-2)th stage buffer; and data management information for the (n-1)th stage buffer. The data output permission signal is generated in response to the data output, and the data is output only when no data is stored in the (n-2)th stage buffer and the (n-1)th stage buffer. data output permission signal generating means for stopping generation of the output permission signal; and recognizing that the final data is to be taken out, cancels the stoppage of generation of the data output permission signal based on data management information of the n-th stage buffer. A first-in, first-out buffer control device comprising means.