KR950014088B1 - Fifo circuit used with general memory - Google Patents

Abstract

an inputting part having a buffer for temporarily storing input data, a delay buffer for storing a delay input, and a selector; a memory bank having an even number memory band for storing the data of an even number address and an odd number memory band for storing the data of an odd number address; an outputting part having a memory band selector for connecting the memory banks, and output registers for reading and storing data stored in the memory bank before a read command is performed; a flag circuit for comparing a read pointer with a write pointer, and showing a data state of the FIFO circuit; and a controlling part for controlling steps to store the data in the memory and output the data.

Description

FIFO circuit using general memory

1 is a block diagram illustrating a typical FIFO structure using dual port memory.

2 is a block diagram showing a FIFO structure using a general memory of the present invention.

3 is a signal flow diagram of a FIFO controller of the present invention.

4 is a read control circuit diagram of the present invention.

5 is a state diagram of a read control circuit according to FIG.

6 is a write control circuit diagram of the present invention.

* Explanation of symbols for main parts of the drawings

101: buffer for temporarily storing the input data 102: delay buffer

103, 301: selector 201: even bank

202: odd bank 302, 303: register

401 flag circuit 500 control block

501 read control circuit 502 write control circuit

503: collision detector 504: read pointer

505: write pointer 506: pointer selector

The present invention relates to the construction of a FIFO memory (First-In First-Out memory) and its circuit.

In general, FIFO uses dual port momory in internal memory cell, but I / O port has equal access authority, but buffering by connecting synchronous circuit that does not allow time delay and asynchronous circuit that allows time delay to FIFO Alternatively, if the circuit is configured for synchronization or temporary storage, one port of the FIFO can be given priority over the other.

In this case, since the internal memory cell of the FIFO can use simple general memory, it is possible to store data with a large area of the same size as compared to the case of using dual port memory.

The present invention prioritizes a read or write port and implements a FIFO that connects synchronous and asynchronous circuits, and a port having a priority can be accessed at any time every cycle, and a non-priority port competes with a port having priority. The goal is to provide an efficient structure by allowing one cycle delay and composing the FIFO using normal memory.

The following describes the invention with reference to the accompanying drawings.

1 is a block diagram showing the general structure of a FIFO.

The general structure of a FIFO is divided into a memory part and a control part.

As the size of the FIFO increases, the size of the memory portion is relatively larger than the control portion.

Most of the FIFO memory section uses dual port memory.

The dual-port memory has independent write and read ports, with separate address decoders for each input and output.

The structure of the FIFO of the present invention is shown in FIG.

In the present invention, access is made while using a general memory instead of a dual port memory used in a general FIFO structure.

And since there is only one address decoder in general memory, one memory module can only write or read at a time, while the number of devices constituting memory cells is smaller than dual port memory, so more data can be stored in the same area and faster. Has access speed.

Accordingly, in the present invention, some logic is added to the general FIFO structure in order to simultaneously perform reading and writing using the general memory.

First, when trying to write to the same memory module in the input part, if the write port has no priority, the part 102 can delay one cycle and the output part can select the memory module used in the read port ( 301) and registers 302 and 303 that read and store data first, and a signal that gives priority to the port in the control unit 500 (PRIORITY) and a signal that informs the current input / output status of the read or write port (READY, VALID). There is a pointer mux 506 that adds the signal and connects the read and write pointers to the designated memory module.

As shown in FIG. 2, the blocks constituting the FIFO are divided into five parts: an input unit (101, 102, 103), an output unit (301, 302, 303), a memory bank (201, 202), a controller (500, 504, 505, 506), and a flag circuit (401).

The memory banks 201 and 202 are composed of two banks and one memory bank is 0, 2, 4, 6,... The even memory bank 201 stores data of an even address consisting of addresses, and the other memory banks are 1, 3, 5, 7,... Is an odd memory bank 202 for storing data of odd addresses.

The input units 101, 102, and 103 are composed of a buffer 101 for temporarily storing input data, a delay buffer 102 for storing a delayed input, and a selector 103.

If the write port has priority, it is connected to the inputs of the memory banks 201 and 202 through the selector 103 without passing through the delay buffer 102.

If there is no priority in the write port, if a conflict occurs due to a read request and a memory bank (201, 202), the input data is delayed one cycle in the delay buffer 102, and the data in the delay buffer 102 is selected in the next cycle. It is connected by 103 and enters memory banks 201 and 202.

In this case, even if there are continuous read and write requests, the read and write requests access different memory banks, so that simultaneous accesses can be made in the same cycle.

The output unit 301, 302, 303 reads and stores the data stored in the memory bank and the selector 301 which connects the memory bank to which the even memory bank 201 and the odd memory bank 202 currently try to read. It consists of output registers 302 and 303.

If the read port has priority, it can be read at any time if there is data in the FIFO.

However, if the read port has no priority, if the write request and the read request data are in the same memory bank, the read request is delayed by one cycle and the read valid bit (VALID) is output as "0".

In the next cycle, the write data accesses different memory banks. At this time, a read request is made, and the next successive read and write requests access different memory banks.

The flag circuit 401 compares the read pointer 504 and the write pointer 505 to indicate a data state in the current FIFO. Usually, the flag circuit 401 generates a signal such as data empty or full.

According to the signal, the circuit connected to the outside of the FIFO can know whether to send next data or read data.

The controllers 500, 504. 505 and 506 have a function of controlling a series of processes of storing and re-outputting data in the memory at the input.

The control unit generates a pointer that specifies the position of the read or write in the memory bank, and generates the timing required for the read or write.

3 is a block diagram of the configuration blocks constituting the control unit of the FIFO and the signal relationship between these blocks.

As shown in FIG. 3, the relationship between the configuration blocks will be described next.

The read pointer 504 is a circuit holding a pointer to data to be read. When the next data read signal RD_EN is applied from the read control circuit 501, the read pointer 504 moves the read data pointer RD_PTR to the next address.

The address of this pointer consists of (P _n-1 …, P ₁ , P ₀ ), (P _n-1 ,…, P ₁ ) is used as the read address of the memory module, and P ₀ is used to select the memory bank. Used.

The write pointer 505 is a circuit holding the pointer WR_PTR for the write data. When the next data write signal WR_EN is applied from the write control circuit 502, the write pointer 505 moves the write pointer to the next address.

The pointer circuits 504 and 505 are implemented with a RING counter.

The memory bank collision detection circuit 503 detects whether the memory bank in which data is currently read is the same as the memory bank in which the write operation is to be performed by the value of P ₀ , the least significant bit of the write pointer 505 and the read pointer 504. It has a function of applying to the read control circuit 501 and the write control circuit 502.

The pointer selector 506 includes a read pointer RD_PTR applied by the read pointer circuit 504, a write pointer WR_PTR applied by the write pointer circuit 505, and a read signal RD_EN applied by the read control circuit 501. And a write signal WR_EN applied from the write control circuit 502 to the memory module having data indicated by the write pointer 505 or the read pointer 504 when there is an active write signal or read signal. It connects the pointer value and generates the memory activation signal RAMEN and the memory read signal WEN necessary for the read or write operation.

At the same time, when the read signal RD_EN is activated, the memory bank selection signal OUT_BANK_SEL to be applied to the selector 301 of the output unit and the data latch signal OUT1_LATCH to be applied to the first output register 302 are generated.

The read control circuit 501 includes an empty signal generated by the flag circuit 401, a read protection signal READ_LOCK generated by the write control circuit 502, a priority R_PRIORITY for the read port, and a memory bank collision signal BANK_CONFLICT. Is received as an input, and when a read signal READ is applied from the input port, the read control circuit determines whether to read data of the next address, and reads the read permission signal RD_EN to the read pointer 504 and the pointer select circuit 506. If the read port is given priority and the current memory bank is in conflict with the write operation, a write protection signal (WRITE_LOCK) is applied to the write control circuit.

4 is a circuit diagram showing the read control circuit in detail.

The data none signal EMPTY and the read protection signal READ_LOCK are inverted to the AND gate A1, and the output of the gate operates as the read preparation signal R_READY.

This R_READY signal is again applied to the AND-OR gate AO2 and the OR-AND gate OA1.

The outputs of the flip-flops D1 and D2 are supplied with a series of AND-OR gates AO1 and AO2 to the OR-AND gates OA1, and the outputs of the AND-OR gates AO1 and AO2 are flip-flops D1 and D2. Is applied to the input of D2).

The output of the flip-flop D1 is applied to the input of the buffer B1, and the output of the buffer is output as the read data valid signal VALID.

On the other hand, the output signal of the OR-AND gate OA1 is applied to the input of the write signal WR_EN and the AND gate A2.

The memory bank collision signal BANK_CONFLICT and the read priority signal R_PRIORITY are applied to the input of the AND gate A2, and the output of the gate operates as the write protection signal WRITE_LOCK.

The inverting input of the READ signal and the output of the flip-flop D1 are applied to the input of the AND gate A3, and the output of the gate is used as the data hold signal OUT2_HOLD of the second register of the output portion.

5 shows a state transition of the read control circuit of the present invention configured as described above.

The operation of the read control circuit will be described below with reference to FIG. 5.

The read control circuit states are classified into four states according to the states of the first register 302 and the second register 303 of the output unit.

The state of SO is when both the first register 302 and the second register 303 are empty, and the state of S1 is when the first register 302 contains valid data and the second register 303 is empty. The state of S2 is when the first register 302 is empty and the second register 303 contains valid data. The state of S3 is that both the first register 302 and the second register 303 are valid. It is filled with data.

Referring to FIG. 5, the state transition that changes according to the input signal is described as follows.

At initialization or when all data in the output register is empty, the state is S0.

At this time, if data enters the memory bank and the read protection signal READ_LOCK does not come from the write control circuit 502, the read signal RD_EN is " 1 " and the state transitions to S1.

In state S1, if the read ready signal R_READY is activated, RD_EN is set to "1" and the data of the first register 302 is moved to the second register 303 and the state transitions to state S3 to fill the register again with the next data. When the R_READY signal is in an inactive state, the RD_EN signal is set to "0" and the data in the first register 302 moves to the second register 303, and the first register 302 transitions to the empty state S2.

If the R_READY signal is inactive in the state S2, if there is a read signal (READ), the state transitions to state S0. If the R_READY signal is activated, the RD_EN signal is set to "1". If the READ signal is present, the state S1. To transition.

In state S3, if the R_READY signal is inactive and there is a READ signal, the state transitions to state S2. If the R_READY signal is activated and there is a READ signal, the RD_EN signal is set to "1" and the data of the second register 303 is read while reading from the memory. The data is kept in the first register 302 and the data in the first register 302 is filled with the second register 303 while maintaining the state S3.

That is, the read control circuit 501 reads and fills the data in the output register first even if there is no data in the FIFO memory, thereby increasing the read speed of the FIFO and reducing the frequency of requesting the same memory bank at the same time.

As shown in FIG. 3 to explain the operation of the write control circuit 502, the write control circuit 502 reads the FULL signal generated from the flag circuit 401 of the FIFO and the read control. When the write protection signal WRITE_LOCK and the write port priority W_PRIORITY and the memory bank collision signal BANK_CONFLICT generated from the circuit 501 are received as inputs, and the write signal WRITE is applied from the input pod, the write control circuit 502 determines whether to write data to the next address, and applies the write permission signal WR_EN to the write pointer circuit 504 and the pointer selection circuit 506, and the delay buffer 102 and the selector 103 of the input unit. The read protection signal READ_LOCK is applied to the delay control signal DELAY_IN and the read control circuit for controlling the control signal.

6 shows a circuit diagram of the write control circuit 502.

The FULL signal from the flag circuit 401 is applied to the inverted signal at the AND gates A5 and A6 and A7, the write protection signal WRITE_LOCK is applied as the inverted signal to the AND gate A5 and the OR gate O1 is applied to the other input of the gate. The output is applied and the output signal of the gate operates as the write permission signal WR_EN.

At the same time, the WR_EN signal is applied to the inverting input of AND gate A5 and the input of AND gate A4.

In addition, the write priority signal W_PRIORITY, the memory conflict signal BANK_CONFLICT, and the write request signal WR_EN are applied to the input of the AND gate A4, and the output of the gate A4 is used as the read protection signal READ_LOCK.

A series of connections consisting of OR gates O1 and AND gates A6 and A7, and flip-flops D3 and D4 are delayed by one cycle when the write request signal (WRITE) is activated but the WRITE_LOCK signal is activated, and thus the write operation cannot be performed immediately. It is a circuit that can perform an operation.

When the write protection signal (WRITE_LOCK) is activated, if the write signal coming through the OR gate O1 fails to perform a write operation by the WRITE_LOCK signal, the output of the AND gate A6 becomes "1", and the flip-flop D3 connected thereto is Delayed by one cycle.

This signal is again applied to AND gate A5 via the input of OR gate O1.

At this time, since the write and read pointers 505 and 504 point to different memory banks, the WRITE_LOCK signal is released and the write request signal WR_EN, which is the output of the gate A5, is activated.

This write request is delayed by one cycle from the pointer selector 506 to enter the write control signal into the memory. At the same time, the output of the flip-flop D3 is delayed by one cycle by the flip-flop D4 and the output of the flip-flop D4 is Create a DELAY_IN signal that is used to write data contained in delay buffer 102 to memory.

As described above, the present invention uses the general memory instead of the dual port memory, so the number of devices constituting the memory cell is small, so that more data can be stored in the same area, thereby achieving faster access speed. .

Claims (3)

A FIFO circuit for connecting synchronous and asynchronous circuits, comprising: an input unit comprising a buffer 101 for temporarily storing input data, a delay buffer 102 for storing a delayed input, and a selector 103; A memory bank comprising an even memory bank 201 for storing even-numbered data and an odd memory bank 202 for storing odd-numbered data; The memory bank selector 301 connecting the even memory bank 201 and the memory bank currently attempting to read the odd memory bank 202 and the data stored in the memory banks 201 and 202 before the read request is read. An output section comprising output registers 302 and 303 for reading and storing; A flag circuit 401 for comparing the read pointer 504 and the write pointer 505 to indicate a data state in the FIFO; FIFO circuit using a general memory, characterized in that the control unit for controlling a series of processes of storing and re-output the data in the memory at the input. The method of claim 1, wherein the output registers 302 and 303 of the output unit are controlled according to the presence or absence of data of a memory module and a collision state of a memory bank to store and maintain valid data in a register before a read operation is performed. FIFO circuit using normal memory, characterized by read control circuitry to indicate whether or not. 2. The method of claim 1, wherein when the input data collides with a memory module in the same cycle as a read operation, the delay buffer 102 and the selector 103 for avoiding the collision are controlled to perform a write operation after one cycle. A FIFO circuit using a general memory, characterized by a write control circuit which allows a signal (READY) to be generated to indicate whether continuous input is possible.