JP2002190747A - Device and method for noise detection - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make an LSI or a product itself self-reset by detecting that the LSI is influenced by external noise. SOLUTION: A fast toggle circuit 20 consists of a flip-flop circuit 23, an inverter 24 and an AND gate 21 for resetting, and the output of the inverter 24 is supplied to one side of a comparator 30. A slow toggle circuit 10 consists of a flip-flop circuit 13, an inverter 24, an AND gate 11 for resetting and a delay element 12, and the output of the inverter 14 is supplied to the other side of the comparator 30. An XCLEAR signal to be supplied through a terminal T11 is a reset signal for initialization. A CLOCK signal to be supplied through a terminal T12 is a signal to be a detection object for detecting the presence/ absence of noise. A DETOUT signal to be outputted from a terminal T13 is the result of discriminating whether the output of the circuit 20 and that of the circuit 10 have the same phase or opposite phases. This DETOUT signal means the absence of noise by its low level and the presence of noise by its high level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a noise detection apparatus and method which can be applied to a countermeasure against a malfunction caused by external noise such as electrostatic noise in a digital signal processing LSI.

[0002]

2. Description of the Related Art Conventionally, external noise such as electrostatic noise is
Digital signal processing LSI (hereinafter simply referred to as LSI)
It causes various malfunctions such as. For example, a camera-integrated VTR (hereinafter referred to as a digital camera) may cause the following malfunction. -The captured image during shooting is not displayed on the liquid crystal panel. The captured image during shooting is displayed on the liquid crystal panel, but when the image recorded on the recording medium is reproduced, it is displayed as black. -A so-called deadlock state occurs in which the controller buttons for recording and playback of the digital camera are not accepted at all.

The cause of these malfunctions is, at most, the LSI clock signal, chip reset signal, or noise entering other necessary signal lines. In the LSI, registers in the LSI are set and controlled by communicating with a control microcomputer (microcomputer) IC for various modes such as a captured image during shooting and an image reproduced from a recording medium. These registers do not always communicate and perform refreshing. Therefore, if incorrect data is set by noise on signal lines required for the LSI, such as a clock signal and a chip reset signal, the registers will malfunction as they are. In many cases, the situation continues.

In the prior art, the following countermeasures are taken for these problems.・ Improve the current drive capability of the output signal of the LSI mounted on the product substrate. • Wire the layout on the board so that it is not susceptible to external noise. As described above, these measures are measures for minimizing the influence of external noise due to electrostatic noise or the like.

[0005]

However, due to the evolution of semiconductor processes and the demand for low power consumption of products, LS
Since the power supply voltage of I decreases year by year, it is becoming weaker against external noise. Further, the increase in the current driving capability of the LSI output signal has already reached its limit at present because of side effects such as interference with other signal lines and unnecessary radiation.

As described above, a device for minimizing the influence of external noise is necessary in the future, but the limit is being seen.
In view of these, in addition to the above-described countermeasures, it is required in the future that the LSI or the product itself can recover by itself when a malfunction occurs due to external noise.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a noise detection apparatus and method which can detect that an LSI has been affected by external noise, and which can recover the LSI or the product itself.

[0008]

According to a first aspect of the present invention, there is provided a noise detecting apparatus capable of detecting noise in a signal, wherein the noise detecting apparatus has a logically identical structure, and one of the delay elements has a delay element. And a comparison means for detecting whether noise is present or not by comparing the output of the first and second toggle means with the output of the first and second toggle means. It is a noise detection device.

According to a fourth aspect of the present invention, there is provided a noise detection device capable of detecting noise included in a signal.
It consists of counting means that increments or decrements in synchronization with the clock, and detecting means that detects that the continuity of the output of the counting means has been disrupted. If the continuity of the output is disrupted, noise is present on the clock line or data line. A noise detection device characterized in that it is determined that the noise has entered.

According to a fifth aspect of the present invention, there is provided a noise detecting apparatus capable of detecting noise included in a signal.
A detection means detects that noise has entered the first signal from a first signal which always has a constant level and a second signal which changes the level only in an initial state, and the noise is detected. A predetermined signal is output from the detection means.

According to a seventh aspect of the present invention, there is provided a noise detection method capable of detecting noise included in a signal.
A delay element is inserted into one of the first and second toggle means, which are logically identical to each other, and the output of the first and second toggle means is compared to determine whether noise is present. This is a noise detection method characterized in that a noise is detected.

According to a tenth aspect of the present invention, in the noise detecting method capable of detecting noise included in a signal, the increment or decrement is performed in synchronization with a clock, and the output continuity of the increment or decrement is disturbed. Is detected, and when the continuity of the output is disturbed, it is determined that noise has entered the clock line or the data line.

According to an eleventh aspect of the present invention, there is provided a noise detection method capable of detecting noise included in a signal, wherein the first signal having a constant level at all times and the level changing only during an initial state are used. A noise detection method characterized by detecting that noise has entered the first signal from the two signals, and outputting a predetermined signal when the noise is detected.

By providing a delay element in one of the first and second toggle circuits and comparing the outputs of the first and second toggle circuits, noise in the signal is detected. Further, by detecting a disturbance in the continuity of the output obtained by incrementing or decrementing in synchronization with the clock, noise entering the clock line or the data line is detected. Further, noise entering the first signal is detected by using the first signal that always has a constant level and the second signal that changes the level only in the initial state. When noise is detected, L
Since the setting of the SI or the product itself can be refreshed, even if the LSI or the product is malfunctioning,
Self-recovery becomes possible.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. Note that the same reference numerals are given to those having the same functions and signals having the same functions throughout the drawings to avoid duplication of description. FIG. 1 shows a clock line noise detecting apparatus according to an embodiment to which the present invention is applied. This noise detection device is composed of two or more toggle circuits. In the embodiment shown in FIG. 1, it is composed of two toggle circuits.

The fast toggle circuit 20 includes a flip-flop circuit 23, an inverter 24, and a reset AND gate 21. The output of the inverter 24 is supplied to one of the polarity comparators 30. Slow toggle circuit 10
Is composed of a flip-flop circuit 13, an inverter 14, an AND gate 11 for reset, and a delay element 12, and the output of the inverter 14 is supplied to the other of the polarity comparators 30.

The difference between the fast toggle circuit 20 and the slow toggle circuit 10 is the presence or absence of the delay element 12 provided in the slow toggle circuit 10. Delay element 12
Is sufficiently delayed that the output of the flip-flop circuit 13 does not exceed the clock cycle.
This is a delay element that reaches the input of No. 3. Therefore,
The Fast toggle circuit 20 and the Slow toggle circuit 10 logically operate in exactly the same manner, but the arrival time from the output to the input of each flip-flop circuit is fast, the Fast toggle circuit 20 is fast, and the Slow toggle circuit is slow. Circuit 10 has the difference that it is slow.

XCLEA supplied via terminal T11
The R signal is a reset signal for initial setting. Terminal T1
2 is a signal to be detected for detecting the presence or absence of noise. The DETOUT signal output from the terminal T13 is a result of the polarity comparator 30 determining whether the output of the Fast toggle circuit 20 and the output of the Slow toggle circuit 10 are in phase or opposite phase.

The operation of the noise detection device will be described with reference to the timing charts of FIGS. CLOCK in FIGS. 2 and 3 is a CLOCK signal supplied to the noise detection device via the terminal T12, and is XCLE.
AR is an XCLEAR signal supplied to the noise detection device via the terminal T11. AND21 output is AND
An output signal of the gate 21, an input of the FF 23 is an input signal of the flip-flop circuit 23, and an output of the FF 23 is an output signal of the flip-flop circuit 23. AN
The D11 output is an output signal of the AND gate 11, and F11
The F13 input is an input signal of the flip-flop circuit 13, and the FF13 output is an output signal of the flip-flop circuit 13.

FIG. 2 shows that when there is no noise on the clock line,
That is, it is a timing chart of each signal in the noise detection device as an example of a normal operation. In cycle 1, XCLE
AR signal changes from low level to high level, Fas
The reset of the t toggle circuit 20 and the Slow toggle circuit 10 is released. Therefore, the fast toggle circuit 20
And the Slow toggle circuit 10 start operating at the same time.

The difference between the operations of the two toggle circuits is that the delay time between the output of the AND gate 21 and the input of the flip-flop circuit 23 is short, and the output of the AND gate 11 and the flip-flop circuit 13 This is a point that the delay time between the input and the input is slow. However, since the amount of delay time until the input of the flip-flop circuit 13 does not exceed the clock cycle, the output of the flip-flop circuit 23 and the output of the flip-flop circuit 13 have the same phase.

The polarity comparator 30 is a fast toggle circuit 2
Since the output of 0 and the output of the slow toggle circuit 10 are in phase, the detection result DETOUT signal keeps outputting a low level. In the DETOUT signal, a low level means no noise and a high level means noise.

FIG. 3 shows that when there is noise on the clock line,
That is, it is a timing chart of each signal in the noise detection device as an example at the time of abnormal operation. CLO of cycle 5 in FIG.
The case where noise is included in the CK signal is taken as an example. The output of the flip-flop circuit 23 of the fast toggle circuit 20 captures a low level at the rising edge of the CLOCK signal at the left end of cycle 5. Then, in the noise portion of cycle 5, at the timing of the time point a of the input of the flip-flop circuit 23, the input of the flip-flop circuit 23 is
Since it is at the high level, the output of the flip-flop circuit 23 is inverted from the low level to the high level.

On the other hand, in the slow toggle circuit 10, the CL
At the timing a in cycle 5 in which the OCK signal has noise, the input of the flip-flop circuit 13 is at a low level due to the influence of the delay element 12, so that the output of the flip-flop circuit 13 is not inverted. As described above, the Fast toggle circuit 20 malfunctions due to the influence of the noise of the CLOCK signal in cycle 5, but the Slow toggle circuit 10
Does not malfunction.

Fast toggle circuit 20 after cycle 6
And the polarity of the output of the Slow toggle circuit 10 are inverted.
The ETOUT signal continues to output a high level with noise. The control microcomputer IC recognizes that the DETOUT signal is at the high level, refreshes various settings of the LSI or the product itself, and resets the Fast toggle circuit 20 and the Slow toggle circuit 10 with the XCLEAR signal. Multiply.

In this embodiment, two toggle circuits are used. However, a method of detecting clock noise by confirming the continuity of an incrementer output that operates in clock synchronization without using the toggle circuit is also available. is there. An example is shown in FIG. Incrementer 31 via terminal T11
Is supplied with a CLOCK signal. In the incrementer 31, the count value is incremented by one in accordance with the CLOCK signal. The count value is supplied to the continuity detection circuit 32. The continuity detection circuit 32 detects whether or not the supplied count value is a monotonic increase that maintains continuity. The detection result is output from a terminal T14 derived from the continuity detection circuit 32 as a DETOUT signal.

As described above, when the CLOCK signal has no noise and the normal operation is continued, the output of the incrementer 31 monotonically increases, but when the CLOCK signal contains noise, a malfunction occurs and the continuity of the output signal is disturbed. There is.
By detecting that the continuity has been disrupted, various settings of the LSI or the product itself can be refreshed.

As an example of detecting the monotonous increase while maintaining the continuity, it may be determined whether or not the gradient of the supplied count value has a predetermined gradient.

Also, a decrementer may be used instead of the incrementer 31. When the decrementer is used, the output of the decrementer monotonically decreases.
When noise is included in the K signal, the continuity of the monotonous decrease of the output of the decrementer may be disturbed. By detecting the disruption of the continuity, various settings of the LSI or the product itself can be refreshed.

Next, as another embodiment, a noise such as a chip reset signal (XRESET signal) which enters a signal line fixed at a high level or fixed at a low level during most of the normal operation is detected. FIG. 5 shows an example of this. In this case, the noise detection device includes an inverter 41, an inverter 42, an AND gate 43, and an OR gate 44.
It consists of. The XRESET signal is supplied via the terminal T21. The XRESET signal is a signal that is fixed at a high level except when the power of the product is turned on. Terminal T
The set signal SET supplied via the line 22 sets the initial state, and the noise detection result DETOUT signal has a low level meaning no noise and a high level means noise.

FIG. 6 is a timing chart of each signal in the noise detecting device when the XRESET signal has noise, that is, when the XRESET signal has an abnormal operation. XRESET in Figure 6
The case where noise enters the signal at the timing of time point b will be described as an example. First, power is turned on, and the XRESET signal is released from a low level to a high level. After that, SET
The signal is once set to the high level, and the noise detection device is set in a detectable state. At that time, the DETOUT signal becomes a low level meaning no noise. When noise enters the XRESET signal, the output of the inverter 42 is inverted due to the influence of the noise, and the DETOUT signal continues to output a high level indicating that there is noise. Thus, this circuit:
The noise of the chip reset signal (XRESET signal) fixed to a high level except when the power of the product is turned on can be detected.

The control microcomputer IC recognizes that the DETOUT signal is at the high level, refreshes various settings of the LSI or the product itself, and raises the SET signal again to the high level, so that the noise detection device can operate. Initialization is performed.

In the circuit shown in FIG. 5, when a plurality of noises enter the XRESET signal and the number of the noises is odd, the DETOUT signal goes to a high level indicating that there is noise. Is an even number, the DETOUT signal goes low, meaning no noise. As a countermeasure against this, as shown in FIG.
The TOUT signal is supplied to the counter 65, the number of changes (rising + falling) of the DETOUT signal is counted, and the NOIS signal is supplied through a terminal T24 derived from the counter 65.
There is a method of transmitting the E_NO signal to a control microcomputer IC or the like.

In this embodiment, the noise detection circuit for the XRESET signal fixed to the high level is described as an example. However, in the case of the signal line fixed to the low level, the signal inverted by the inverter is converted to the XRESET signal in FIG. Just connect to it.

In this embodiment, the Slow toggle circuit 1
Although the delay element 12 is connected to the output terminal of the AND gate 11 of 0, the delay element may be connected to the input terminal of the AND gate 11. For example, with the inverter 14,
A delay element may be provided between the AND gate 11.

[0036]

According to the present invention, a clock signal of an LSI or the like, a chip reset signal, or noise of a signal line necessary for operation is detected, and the LSI or the product relating to the signal line or the product itself malfunctions. The possibility can be recognized. Since this information can be obtained, the settings of the LSI and the like set by the control microcomputer and the like and the data in the RAM can be refreshed, so that the product can recover from a malfunctioning state by itself.

According to the present invention, the output of the fast toggle circuit and the output of the slow toggle circuit, which are logically substantially the same except that a delay element is provided, are compared with each other, so that the noise included in the clock signal is obtained. Can be detected. When noise is detected from the signal, the LSI
Alternatively, since the setting of the product itself can be refreshed, even if the product is in a malfunctioning state, it is possible to self-recover.

Further, according to the present invention, it is possible to detect noise on a clock line or a data line by detecting a disturbance in continuity of an output obtained by incrementing or decrementing in synchronization with a clock. Can be. Then, when noise is detected from the signal, the setting of the LSI or the product itself can be refreshed, so that even if the product is in a malfunction state, it is possible to self-recover.

Further, according to the present invention, it is possible to detect the noise included in the chip reset signal by using the chip reset signal which always has a constant level and the set signal which changes the level only in the initial state. it can. Then, when noise is detected from the signal, the setting of the LSI or the product itself can be refreshed, so that even if the product is in a malfunction state, it is possible to self-recover.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of a clock signal noise detection device according to the present invention.

FIG. 2 is a timing chart of an example of a normal state according to the present invention.

FIG. 3 is a timing chart of an example of an abnormal state according to the present invention.

FIG. 4 is a block diagram of another example of the clock signal noise detection device according to the present invention.

FIG. 5 is a circuit diagram of one embodiment of a chip reset signal noise detection device according to the present invention.

FIG. 6 is a timing chart of an example of an abnormal state according to the present invention.

FIG. 7 is a circuit diagram of another embodiment of a chip reset signal noise detection device according to the present invention.

[Explanation of symbols]

10 ... Slow toggle circuit, 20 ... Fast toggle circuit, 11, 21 ... AND gate, 12 ...
Delay element, 13, 23... Flip-flop circuit, 1
4, 24 ... Inverter, 30 ... Polarity comparator

Claims (12)

[Claims] 1. A noise detection device capable of detecting noise included in a signal, comprising: a first and a second toggle means having logically the same configuration, one of which has a delay element inserted therein; A noise detecting device comprising: comparing means for comparing the outputs of the first and second toggle means to detect whether noise is present or not. 2. The apparatus according to claim 1, wherein when the comparing means detects that the signal has noise, a circuit or a device receiving the signal is refreshed to avoid a malfunction. The noise detection device as described in the above. 3. The first toggle means comprises: a first AND gate to which an input signal is supplied; and a first flip-flop to which an output of the first AND gate is supplied. The second toggle means includes a second AND gate to which the input signal is supplied, and a second flip-flop to which an output of the second AND gate is supplied. 2. The noise detection device according to claim 1, further comprising a delay element that applies a predetermined delay to one of an input terminal and an output terminal of the AND gate. 4. A noise detection device capable of detecting noise included in a signal, a count means for incrementing or decrementing in synchronization with a clock, and a detection means for detecting that the continuity of the output of the count means has been disrupted. A noise detecting device, wherein when the continuity of the output is disturbed, it is determined that noise has entered the clock line or the data line. 5. A noise detection device capable of detecting noise included in a signal, comprising: a first signal having a constant level at all times; and a second signal having a level changed only in an initial state. 1. A noise detecting apparatus comprising: detecting means for detecting that noise is included in one signal; and when the noise is detected, a predetermined signal is output from the detecting means. 6. The apparatus according to claim 5, further comprising counting means for counting a change in an output signal of said detecting means.
2. The noise detection device according to 1. 7. A noise detection method capable of detecting noise included in a signal, wherein a delay element is inserted into one of the first and second toggle means having the same logical configuration. A noise detecting method, comprising detecting whether noise is present or not by comparing the outputs of the first and second toggle means. 8. The circuit according to claim 7, wherein when the comparison result indicates that the signal has noise, a circuit or a device receiving the signal is refreshed to avoid a malfunction. The described noise detection method. 9. The first toggle means comprises: a first AND gate to which an input signal is supplied; and a first flip-flop to which an output of the first AND gate is supplied. The second toggle means includes a second AND gate to which the input signal is supplied, and a second flip-flop to which an output of the second AND gate is supplied. 8. The noise detection method according to claim 7, further comprising a delay element that applies a predetermined delay to one of an input terminal and an output terminal of the AND gate. 10. A noise detection method capable of detecting noise included in a signal, wherein the increment or decrement is performed in synchronization with a clock, and that the continuity of the output of the increment or decrement is detected and the output is detected. A noise detection method characterized by determining that noise has entered a clock line or a data line when the continuity of the data has been disturbed. 11. A noise detection method capable of detecting noise included in a signal, comprising: a first signal having a constant level at all times; and a second signal having a level changed only in an initial state. 1. A noise detection method, comprising: detecting that noise is included in one signal; and outputting a predetermined signal when the noise is detected. 12. The noise detection method according to claim 11, further comprising counting means for counting a change in the predetermined signal.