JPS6025086A - Digital vtr switching control circuit - Google Patents

Abstract

PURPOSE:To prevent previously disorder of a reproduced picture by discriminating whether VTR is switched by a VTR switching discriminating circuit and by stopping replacing operation of address data and ID signal data for a specified time by a replacing stopping circuit through a discriminated output. CONSTITUTION:A gate circuit 21 is installed in a replacing control signal line from a replacing control circuit 17 to a data replacing circuit 14, and the output S12 of a switching discrimination circuit 22 as its OFF control signal S11 is obtained through an invertor 23. The switching discrimination circuit 22 receives a switching detection signal S13 which is fallen to a logic level L when a VTR switching switch 24, which is installed to a digital video signal processing circuit, is operated. The signal S12 of the logic H level which is composed of pulses with the prescribed pulse width is obtained when the logic level of a frame pulse S14 is changed after the arrival of the detection signal S13. This signal S12 is inverted by the invertor 23, and supplied to the gate circuit 21 as a closing control signal S11 of the logic L level, thereby making this gate circuit 21 closed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital VTR switching control device, and more particularly, to a digital VTR switching control device, which controls switching of a plurality of composite recording type VT1'Ls (video tape recorders) and outputs necessary video signals. This allows selective recording or reproduction.

[Background technology and its problems]

The first conventional digital VTR switching control device of this type.
The structure shown in the figure is used. That is, a plurality of composite recording system VTRs, for example, four VTRs 1 to 4,
A switching control circuit 5 is provided in common to the switching control circuit 5, and the VTRs 1 to 4 are connected to the digital video signal processing circuit 6 of the switching control circuit 5 via an interface 7.

Here, the digital video signal processing circuit 6 provides, via the interface 7, a reference signal S1 consisting of a composite synchronization signal for servo operation of each VTR 1 to 4, and also provides digital video signal data DIN for recording. The digital video signal processing circuit 6 also processes the digital video signal data reproduced from the VTRs 1 to 4 via the interface 7 and the operating mode (
Stop, play, record.

Output data D consists of operation mode data representing (fast forward, 2 rewind, etc.). Take UT. Thus, the digital video signal processing circuit 6 is configured to exchange digital video signal data while being controlled by the control signal S1 according to the operation mode of the VTRs 1 to 4.

Further, the digital video signal processing circuit 6 receives an external analog video input signal AV 1N and an audio input signal AV 1N.
@After receiving AD1N and performing digital conversion processing, V'l
"It is possible to record to R1 to R4, and v'rgi
The data read from ~4 is converted into an analog video output signal AV.
oUT so that it can be output to a monitor, for example, and further transmits the digital video data read from v'rn, i to 4 as is to an external device as a digital video output signal DvoUT, and outputs the digital video from the external device. Receiving input signal DV□, VT
It is designed so that it can be recorded on R1 to R4.

Here, the format shown in FIG. 2 is used for the digital video signals recorded on the VTRs 1 to 4. That is, a video signal converted from an analog video signal to a digital signal is blocked into a large number of blocks BL having a predetermined number of samples after rearranging the data in a predetermined manner at predetermined intervals as a measure against dropout. As shown in FIG. 2, the contents of the signals of each block are as follows: First, a block synchronization code DT indicating that the block BL starts.
I is inserted. Next, a confirmation signal (
(hereinafter referred to as an ID signal) and a data signal DT2 containing the block address assigned to the block are inserted. Here, the ID signal includes a frame ID representing the frame number of the original screen, a field ID representing the field number within this frame, and a line II) representing the line number within this field.
and a channel ID representing a channel number. Following this data DT2, video signal data DT3 of the block is inserted, and then parity code DT4 used for error correction and audio data DT5 are sequentially inserted. Digital data in such a data array is modulated with a block code that does not include a C component, such as 8/9 NRZi conversion (consisting of a no-return zero code), and is recorded on the tapes of the video table recorders 1 to 4.

The digital video signal data recorded in this manner is used as digital video signal data l) during playback. The data is transferred as UT to the digital video signal processing circuit 6 through the interface 7, demodulated and corrected by the time axis correction circuit, and then the data distributed during recording is rearranged to the original time sequence, and then error correction is performed. After that, the digital video (digital video) is written and stored in a frame memory provided in the M processing circuit 6. When the data in this frame memory is sent as an analog signal to a monitor, for example, the data read from the frame memory is After digital-to-analog conversion, a synchronization signal is added and sent out as an analog video output signal AVoUT.On the other hand, when sending out as a digital signal, the contents of the frame memory are directly converted into a digital video output signal DVoUT.
Sent as T.

By the way, when the digital video signal processing circuit 6 performs time axis correction on the data read out from the VTRs 1 to 4 in this way, the digital video signal processing circuit 6 uses the output data signal. If the ID signal data and block address DT2 inserted in the UT (Fig. 2) are damaged due to dropout, for example, replacing the ID signal data and block address is practically necessary to correct this. A flywheel circuit predicts an ID signal and block address that are likely to correspond to the block based on the ID signal and address data corresponding to the blocks before and after the block and the previous frame or field, and the prediction result is calculated. The data portion of the data D112 in the format shown in FIG. 2 is replaced by using the data D112 as the ID signal and block address of the block. Here, the length of the data BL for one block in FIG. The data recorded in the frame memory by the operation of the circuit has a field II) indicating that they are the same field.
” You will be kicked. The data output signal that has been reproduced for this. If the frame number of the UT changes, the flywheel prediction result will also follow the change in the field number if the range of block data used for prediction by the flywheel circuit passes, so the ID stored in the frame memory will change. The signal will also follow the change in frame number.

[Time axis correction circuit in Fig. 3] At 0, the interface x −
, Sickness that is present is corrected. The output data from the memory terminal is sent out as the output of the time axis 'rn: positive circuit via the data I1 pinch circuit 14 and further via the buffer circuit J5.

Also, ID signal data and pronk address signal DT2 of the town digital data provided via the buffer circuit 1g1l are provided to the flywheel circuit 16. As described above, the flywheel circuit 16 performs predictive calculation of the ID signal data and block address of the block on the apron digit (b) data read from the memory 12, and provides the calculation result to the data 41 conversion circuit 14. The data conversion circuit 14 is controlled by the data conversion control circuit 17 and converts the data read from the memory 12 into data.
Unless the contents of the D signal and the block address DT2 are inconsistent with the predicted data sent from the flywheel circuit 16, the predicted data arriving from the flywheel circuit 16 is replaced at the position of the current sales data DT2. Thus, for example, if the ID signal data and block address DT2 are corrupted due to dropout, this can be corrected by the predicted data of the flywheel circuit 16.

In the digital video signal processing circuit 6 having the time axis correction circuit 10 configured as described above, when attempting to switch and control the digital data of the VTRs 1 to 4, one VTR
When switching from a state in which reproduced digital data is received from a TR to a state in which reproduced digital signals from another VTR are received, there is an inconvenience that the reproduced screen is temporarily disturbed due to the color frame being disturbed. Incidentally, when recording and reproducing a standard television format video signal as a composite signal consisting of a luminance signal and a color signal, it is necessary to maintain the continuity of the color frame due to the change in the phase of the burst signal in the main field. Unless processed properly, extreme color shifts will occur on the screen at discontinuous points in the color frame. For example, in the case of an NTSC television signal, the number of color frames is circulated with four fields as one cycle. For example, at time t1 in FIG.
Suppose you switch to TR2. VT at this point t□
A color frame of digital video output data coming from RI and VTR2 is a frame ID signal FMID.

(Fig. 4 (Al)) and FMID2 (Fig. 4 (Bl))
) and field ID signal FLID□ (Fig. 4 (A2)
) and FLID2 (FIG. 4 (B2)). In the case of FIG. 4, the color frame at time t1 of the digital video output data of the VTRI switches from color frame "4" to color frame 11, whereas the color frame of the digital video output data of the second VTR2 switches from color frame "4" to color frame "11". It is in the state of switching from frame "2" to frame "13". Therefore, at time t1 the first V
From the digital video output data of TR1 to the second VTR
When switching to the video output data of 2, the color frames of the reproduced video data are as shown in Fig. 4 (C1) and (C2).
Frame ID signal FMIDP and field ID shown in
As shown by signal FLIDP, the color frame at time t1 results in a switch from color frame "4" to color frame "4".

In this case, the color frames of the reproduced video output data become discontinuous at time t1. In other words, considering the cyclic nature of color frames, color frame ``4'' should be followed by color frame ``color frame RO'', but this is not the case. By the way, the probability that the color frames of the reproduced video data become discontinuous in this way at the time of VTR switching is 1/2. Incidentally, VT, which is a control symmetry
The servo system of R1 to R4 is configured to operate in frameronc mode based on the reference synchronization signal, and therefore the switching operation in the digital video signal processing circuit 6 is performed based on the first and second field sets for the incoming video data. A set of third and fourth fields is used as a unit, and a switching operation is performed when the data of the unit is completed. Therefore, at time t1, the probability of the continuity of the color frames of the used data before and after switching is 1/2 whether they match or not.

By the way, the flywheel circuit 16 of the time axis correction circuit (FIG. 3) performs a dropout correction operation not only when continuity is maintained, but also when continuity is not maintained.
Even though the color frames of the reproduced digital data become discontinuous at the time t1, the color frames of the reproduced video data are the fourth
As shown in FIGS. (Dl) and (D2), during a period T1 after the elapse of time t0, it is assumed that the continuous reproduction frame ID signal FMIDP and field ID number FLIDP continue to arrive, and the data input circuit 14 This means that one-time conversion data will be supplied to the user. However, during this period T1, the color signal and luminance signal data sent from the memory 12 to the data input circuit 14 are the data after switching, so ID signals and addresses that are unrelated to the data after switching are replaced. If this problem is left unaddressed, the video data cannot be written to the correct position in the frame memory provided at the subsequent stage, and the reproduced image will be distorted.

The operation of the flywheel circuit 16 is such that when the reproduction digital data is switched after the period T1 has passed and the data necessary for the predictive calculation arrives at the flywheel circuit 16, the flywheel circuit 16 thereafter changes the data after the switching. Since the prediction calculation result executed based on t1 is sent as A1 conversion data to the data I1 conversion circuit 14, the range in which the image is actually disturbed is within one field section after time t1, but in such a short time. Even if the image is distorted, it is very annoying as an image on a monitor screen.

[Purpose of the invention]

The present invention has been made with the above points in mind, and even if the color frames become discontinuous when switching the video signals coming from each VTR in the digital video signal processing circuit 6, the image will not be distorted. The aim is to make it possible to effectively avoid such occurrences.

[Summary of the invention]

In order to achieve such an object, in the present invention, when the VTR is switched, this is determined by a VTR switching discrimination circuit, and based on the discrimination output, the switching operation of ID signal data and address data is stopped by a switching stop circuit for a predetermined period of time. In this way, the color signal and luminance signal data after switching, as well as the ID signal data and address data attached to them, are changed to 1! Then, send it as playback data.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings. Third
As shown in FIG. 5 with the same reference numerals assigned to the corresponding parts, the digital VTR switching control circuit according to the present invention has a configuration including a switching control circuit as shown in FIG. 5 as a time axis correction circuit 10. Use the one. In other words, replacement control circuit 1
A gate circuit 21 is provided on the exchange control signal line from 7 to the data exchange circuit 14, and the output 812 of the switching discrimination circuit n is obtained as the off control signal 811 through an inverter n. The switching determination circuit n is a digital video signal processing circuit 6.
When this switch U is operated, a switching detection signal 813 which falls to the level of, for example, a logic mountain is received from the VTR changeover switch gu, which is installed in FIG. At the point in time when the logic level of 814 changes, a logic (1) U level switching determination signal 812 consisting of a pulse with a predetermined pulse width is obtained. This switching determination signal 812 is inverted at the inverter B and the logic 11. It is applied to the gate circuit 21 as a closing control value +-1Su of the J level to close the gate circuit 21.

In the above configuration, the digital video signal processing circuit 6
When the VTR selector switch 6 is manually switched, for example, at time t2 in FIG.
, the switching determination circuit 22 generates a switching permission signal S15 as shown in FIG. 6(C), and sends out a switching permission signal (D)). By thus closing the gate circuit 2, the data exchange operation in the data exchange circuit 14 is stopped. Here, the switching determination signal 812 indicates that the frame ID data FMIDP after reproduction is the same as that of the flywheel circuit 16.
The frame pulse 814 is reset two frames later so as to include the period T1 disturbed by the flywheel operation.

Note that the rise of the switching determination signal S12.0 in FIG. 6(D) corresponds to the VTR switching time t□ mentioned above in FIG. 4, and therefore the operation of the VTRI is stopped, which is indicated by the stop signal VTRI in FIG. ), and the operation of the VTR2 starts (indicated by the stop signal VTR2 in FIG. 6(F)).

In this way, the reproduced digital data read out from the memory 12 after switching passes through the data switching circuit 14 as it is during the rising period of the switching determination signal S12.
Eventually, the rising period of the switching determination signal 812 passes and the gate circuit 21 opens, thereby opening the data switching circuit 14.
is now controlled by the replacement control circuit 17, and thereafter the data output from the flywheel circuit 16 will be replaced with the data read from the memory 12. At this time, the output data of the flywheel circuit 16 performs a predictive calculation operation based on the reproduced digital data after switching, as described above with reference to FIG. Since they have matching contents, the original drop correction operation can be executed.

On the other hand, the ID of the video data output through the data conversion circuit 14 while the gate circuit 21 is in the closing operation.
(Since the M number and block address were attached to the reproduced digital data after switching, they match the video data.

As described above, if 4:1°I is implemented, image distortion can be easily prevented by adding a replacement control circuit with a relatively simple configuration on the same board as the time axis correction circuit 10. By the way, if you try to solve this problem based on the conventional way of thinking, it will be complicated, such as adding a special board or inputting a subcarrier to lock the color frame. It is unavoidable that some modification will be required.Also, doing this means using the same processor and VTR, changing the board setting constants, and changing the board in order to provide multiple functions with minimal modification. It is inappropriate to apply this method to composite digital VTRs such as 4fsc and 3fsc, component digital VTRs such as 2-1-1, etc. by simply replacing the .

〔Effect of the invention〕

As described above, according to the present invention, in the time axis correction circuit, I
In a device that predicts D signal data and address data from reproduced digital data and replaces this predicted data with video data, it determines that the VTR has been switched and stops the switching operation for a predetermined period. By doing so, it is possible to prevent a mismatch between the video data after switching and the ID signal and address data, thereby preventing disturbances in the reproduced image. In doing so, it is only necessary to add a relatively simple configuration to the conventional configuration. Incidentally, although the time axis correction circuit can actually be constructed on 11 IC boards, the structure of the present invention can be formed on the same board, so the overall structure does not need to be complicated.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a digital VTR switching control circuit to which the present invention is applied, and FIG. 2 is an I11 diagram showing the format of digital data recorded on the VTR.
? ) diagram, Fig. 3 is a block diagram showing a conventional time axis correction circuit, Fig. 4 is a signal waveform diagram showing the signals of each part, and Fig. 5 is a block diagram showing the conventional time axis correction circuit.
The figure is a block diagram showing a time axis correction circuit which is a connected part of the digital VTR switching circuit as an embodiment of the digital VTR switching circuit according to the present invention, and FIG. 6 is a signal waveform diagram showing signals of each part thereof. 1 to 4... VTJ5... switching control circuit, 6... digital video signal processing circuit, 7... interface, 10... time axis correction circuit, 11, 15... buffer circuit, 12... ...Memory, 13...Address control circuit, 14...1 with data (circuit, 16...Flywheel circuit, 1q...Conversion control circuit, Addition...Ima) conversion stop circuit. Procedure Written amendment dated April 2, 1982, by Kazuo Wakasugi, Commissioner of the Japan Patent Office, History 1, Indication of the case, Special Request for Proposal No. 133119 of 1982, 2, Name of the invention, Digital VT R9J conversion control circuit 3, Make amendments. Relationship with human intelligence Patent applicant address Higashi Kabuto■ S Shininyo Ward Kitashinyo 6-7 A name (21
8) Sony Corporation Representative Norio Oga 4, Dai Buri 150 ('a talk 03-470-659)
1) Address: 3-22-10-6, Jingumae, Shibuya-ku, Tokyo, Contents of amendment (1) Statement, 4th negative] line, insert "and digital audio" before "Deba signal". (2) 10-1, 4th negative 3rd line, 1 and digital audio before 1-Person B. (3) Same, in the 6th negative 7th line, after ``the content of'' is inserted ``after being rearranged in chronological order''. (4) Same, 16th negative lines 8 to 11, corresponds to [, and is therefore indicated by .... '' corresponds to ``J and H'' Correct. (5) Same, 17th negative 5th line, insert ``1 out'' next to ``-Drotz''. (6) Same, y4isB3b, r 4 fBO+ 3f
Delete "sa" etc. (7) Same, page 18, line 4, delete "[2-1-], etc." (8) Correct the tracing in Figure 6. (9) Specification, page 5, lines 5-7, after the insertion of “°°
are inserted sequentially. ” is corrected as follows. "After the audio data DT4 and the error d
The parity code DT5 used for J is sequentially inserted. ” Eyelids −−〜 〜

Claims (1)

[Claims] By selectively switching a plurality of VΦRs, the reproduced digital data sequentially arriving from the switched VTR is stored in the memory, and the I included in the reproduced digital data is stored in the memory.
D signal data and address data are sequentially received, ID No. 4 data and address data that should be included in the data stored in the memory are predictively calculated, and the corresponding stored data is read from the memory based on the result of the predictive calculation. When the stored data is replaced with ID signal data and address data and sent out,
A digital VTR switching control circuit, characterized in that the TR switching control circuit comprises a switching stop circuit having a switching inhibiting circuit section that allows the VTR to increase the switching operation of the ID signal data and address data for a predetermined period of time. control circuit. 1