JPS62279756A - Data transfer system - Google Patents

Abstract

PURPOSE:To share a signal line by a transmission side, and a reception side, to send data by the transmission side according to the command of the reception side, and to unify the signal line of a system, by providing a pull-up resistance at the signal line connected to each open collector circuit in a transmission part, and a reception part. CONSTITUTION:A reception part 2, and a transmission part 3 are connected with a signal line 1, and a positive power source voltage V is impressed on both ends of a pull-up resistance R provided at the signal line 1. A clock CL is added on an open collector circuit 21, and a shift register 23 in the reception part 2, and a NOT circuit 22 which identifies a signal S1 from the transmission part 3, is provided between the connection point of the signal line 1 and a circuit 3, and the input terminal IN of the register 23. Also, an open collector circuit 35, and a non-inversion gate circuit 31 in the transmission part 3 are connected to the signal line 1, and the signal line 1 is shared by the transmission part 3, and the reception part 2, and the transmission part 3 sends the signal S1 by the command from the reception part 2.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a data transfer method, and particularly to a data transfer method in which a transmitter sends data in response to a command from a receiver.

[Conventional technology]

A commonly used data transfer method is that when the receiving side issues a clock signal, the transmitting side detects this via a signal line and sends out data in synchronization with the detected clock signal.

FIG. 2 is a block diagram showing an example of such a conventional data transfer system.

In FIG. 2, 4 and 5 are shift registers having a number of stages equal to the number of bits constituting one word of the data D1 to be transferred, and 1 and 6 are signal lines.

Each bit of one word of data D1 is written in parallel to each stage from the input terminal IN of the shift register 5 on the transmission side.

When the clock signal CL generated on the receiving side is transmitted to the transmitting side via the signal line 6 and inputted to the clock terminal CLK, the shift register 5 uses the clock signal CL as a reading timing to sequentially output the stored contents of each stage to the output terminal OUT.
Each read bit is transmitted to the shift register 4 on the reception side via the signal line 1. The shift register 4 sequentially writes each bit input to the input terminal IN into each stage using the clock signal CL as a write timing.

When all stages are written, the memory contents of each stage are output to the output terminal OUT.
are read out in parallel to become data D1.

The conventional example shown in FIG. 2 has been explained above: When the clock signal CL is generated on the receiving side, the data D1 is transferred from the transmitting side to the receiving side, one line is used for data transmission, and one line is used for transmitting the clock signal CL. A total of two signal lines are required.

[Problem to be Solved by the Invention 9] As explained above, the conventional data transfer method has the disadvantage that two signal lines are required for the transmitting side to send data in response to a command from the receiving side. be.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks and provide a data transfer system in which a transmitting side sends data in response to a command from a receiving side using only one signal line.

[Failure to solve the problem]

In the data transfer method of the present invention, a signal line is connected to a power source at a first potential via a pull-up resistor, and an output end is connected between the first end of this signal line and a power source at a second potential. a first open collector circuit that is connected and inputs a clock signal;
identifying the potential of the first end of the signal line at a first timing when the clock signal changes from a second state close to the second potential to a first state close to the first potential; a receiving means comprising: an identifying means; and the first timing of the clock signal starts at a second timing when the potential at the second end of the signal line changes from the first state to the second state; rectangular wave generating means for outputting a rectangular wave signal that ends later than expected; storage means for storing at least one data bit and outputting the data bits one by one using the second timing as a read clock;
A composite signal in which the data bit read by the storage means is in the first state and is in the first state during a period in which the rectangular wave signal is output, and is in the second state in other periods. a second open collector circuit that receives the synthesized signal and has an output end connected between the second end of the signal line and a power source at the second potential. and means.

〔Example〕

The present invention will be described in detail below with reference to drawings showing embodiments.

FIG. 1 is a block diagram showing an embodiment of the data transfer method of the present invention.

The embodiment shown in FIG. 1 includes a signal line 1 to which a positive power supply voltage +V is applied via a pull-up resistor, and a receiving section 2 and a transmitting section 3 connected to both ends of the signal line 1, respectively. It is configured as follows. The potential of signal line 1 is assumed to be signal S1.

The receiving section 2 receives the clock signal CL, has an open collector circuit 21 whose one output end is connected to the signal line 1, and whose other output end is grounded, and whose input end is connected to the signal line 1 and receives the signal S5. The NOT circuit 22 has a number of stages equal to the number of bits constituting one word of the data D1, inputs the signal S5 to the input terminal IN, inputs the clock signal CL to the clock terminal CLK, and inputs the clock signal CL from the output terminal OUT. The shift register 23 outputs data D1.

The transmitter 3 includes a non-inverting gate circuit 31 whose input end is connected to the signal line IK, a monostable multivibrator 32 which inputs the output of the non-inverting gate circuit 31 and outputs a signal S2, and the same number as the shift register 23 has. data D1 is input to the input terminal IN, and the clock terminal CLK K
Input the output of the non-inverting gate circuit 31 and connect it to the output terminal OUT.
Shift register 33.1 outputting signal S3 from ! :
, (AN which inputs the N number S2-83 and outputs the signal S4
It is configured to include a D circuit 34 and an open collector circuit 35 which inputs the signal S4, has one output end connected to the signal line 1, and has the other output end grounded.

FIG. 3 is a time chart for explaining the operation of the embodiment shown in FIG.

The clock signal CL has a period Tc and a timing t
1] and rises at timing t2.

Immediately before timing 1, the clock signal CL is at a high level, so the signal line 1 is discharged by the open collector circuit 21), and the signal SIH is at a low level. The output impedance of the open collector circuit 21 changes from low impedance to high impedance at timing tl, the signal line 1 begins to be charged with the power supply voltage +■, and after the delay time T elapses, timing t3
At this point, the signal S1 becomes high level.

Since the non-inverting gate circuit 31 receives the signal S1, its output rises at timing 1.

The monostable multi-bi break 32 is a non-inverting gate circuit 31
It outputs a signal S2, which is a series of rectangular waves, which rises at timing t3 and falls at a delay time T2 later than timing t2. However, the delay time T2 is set shorter than the period during which the clock signal CL is at a high level. The signal S2 becomes a repetitive signal whose repetition period is equal to the period Tc, as shown in FIG.

The shift register 33 stores 1 of the data D1 written in each stage.
Each bit of one word is sequentially read out at the rising timing of the output of the non-inverting gate circuit 31, that is, timing t3, and is outputted as a signal S3. For each bit of data D1, logic "'1# corresponds to high level and logic "O# corresponds to low level, and the bit string read out as signal S3 is...'"1". 0”・
0"・1N..., the signal S
3 as shown in FIG.

The AND circuit 34 combines the signals S2 and S3 and outputs it as a signal S4 shown in FIG.

Since the open collector circuits 21 and 35 are connected in parallel to the signal line l, the signal S1 is the negative sum of the clock signal CL and the signal S4. Therefore, in each time slot 11 of the signal S3 (each time slot between two consecutive timings 13) in which the signal S3 is at a high level, the leading timing t
3, the signal line 1 (which had been charged) begins to be discharged and remains discharged until the next timing 11.

In a time slot in which the signal S3 is at a low level, the signal line 1 remains charged from the first timing t3 to the next timing t2, and this timing t
At 2, the signal line 1 begins to be discharged, and at the next timing t
It was discharged to 1! There are up to 2. As a result, the signal S1 becomes as shown in FIG. 3 in response to the signal S3.

The NOT circuit 22 identifies and inverts the signal S1, and outputs it as a signal S5 shown in FIG. Signal S5 is signal 8
Timing t during the time slot where 3 is high level
The signal 83 becomes high level at timing t2, and the signal 83 becomes low level at timing t2 during the real-time slot.

The shift register 23 sequentially writes the signal S5 to each stage using the rising timing of the clock signal CL, that is, the timing t2, as the write timing, and when all stages have been written, the stored contents of each stage are read out as data D1. .

In the embodiment shown in FIG. 1, as explained above, when the clock signal CL is generated in the receiving section 2, the data D1 is transferred from the transmitting section 3 to the receiving section 2, and only one signal line is required.

In the embodiment shown in FIG.
1 is identified and inverted, but only the identification operation is essentially necessary, and the inversion operation is not necessarily required. NOT If a non-inverting gate circuit (outside of the circuit 22) is used, the receiving section 2
The data output by is the data D1 read by the transmitter 1.
The data will be inverted. Further, in the embodiment shown in FIG. 1, a pull-up resistor R is provided at the end of the signal line 1 on the transmitter's3 side and the end on the receiver section 2 side, but one of these may be omitted.

Although the present invention has been described above in detail with respect to the case where a positive power source is used, the present invention is also applicable to the case where a negative power source is used.

〔Effect of the invention〕

As explained in detail above, the data transfer method of the present invention is
A signal line for transferring timing information of a clock signal generated by the receiving section as a data transfer command to the transmitting section, and a signal line for transferring data information output by the transmitting section to the receiving section in response to this transferred timing information. Since they are shared in common, there is an effect that only one signal line is required.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the data transfer method of the present invention, FIG. 2 is a block diagram showing an example of the conventional data transfer method, and FIG. 3 explains the operation of the embodiment shown in FIG. 1. This is a time chart for 1...signal line, 2...--receiving section, 3...
...Transmission section, 21, 35...Open collector circuit, 22...NOT circuit, 32...
... Monostable multivibrator, 33...Shift register, 34...AND circuit, R...
...Pull-up resistor. Agent Patent Attorney Uchihara ``2nd son of Jinyo

Claims (1)

[Claims] A signal line connected to a power source at a first potential via a pull-up resistor, and an output end connected between the first end of this signal line and a power source at a second potential. a first open collector circuit into which a clock signal is input; and a first open collector circuit that inputs a clock signal, and a first timing when the clock signal changes from a second state close to the second potential to a first state close to the first potential. a receiving means comprising: an identification means for identifying a potential at the first end of the line; and a second timing at which the potential at the second end of the signal line changes from the first state to the second state. rectangular wave generating means for outputting a rectangular wave signal starting at and ending later than the first timing of the clock signal; storing at least one data bit and using the second timing as a read clock to read the data bit; Storage means outputs one by one, and the data bits read by the storage means are in the first state during a period in which the rectangular wave signal is output, and during other periods, the data bits are in the first state. a synthesizing means for outputting a synthesized signal that is in the second state; and a synthesizer that receives the synthesized signal and has an output end connected between the second end of the signal line and a power source at the second potential. 1. A data transfer method comprising: a transmitting means having two open collector circuits;