JP2619167B2 - I / O control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output control circuit for selecting an input / output state of an input / output circuit whose terminal is shared with an input / output port by using each bit value of a control register.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram showing a configuration of a conventional serial I / O control circuit incorporating two 8-bit clock synchronous serial I / Os. In the figure, reference numeral 1 denotes a serial I / O having a built-in normal transfer function and automatic transfer function and switching between the two, and reference numeral 2 denotes a serial I / O having only a normal transfer function.

The input / output terminals 110, 11 of the serial I / Os 1, 2
1, 112, 113, 214, 215, and 216 are shared with input / output ports, and it is determined whether to use them as input / output ports or serial input / output terminals by a serial I / O 1 described later.
It is selected by each bit value of the control register 61 and the serial I / O2 control register 62.

[0004] The serial I / O 1 includes a 32-byte SI / O automatic transfer RAM 14, an SI / O automatic transfer data pointer 15, a serial I / O automatic transfer controller 16 and a 5-bit counter for the automatic transfer mode. The configured automatic transfer interval register 17 is connected.

FIG. 2 is a diagram showing the bit configuration of each of the serial I / O 1 control register 61 and the serial I / O 2 control register 62. The bit configuration of the serial I / O 1 control register 61 shown in FIG.
1,2 Internal synchronous clock selection bits are used to set the synchronous clock oscillation frequency when the internal clock selection, bit 3 input ports _{(P 1, P 2, P} 3) to use the serial output terminal S _OUT or clock input as serial I / O 1 port selection bits for selecting whether to use as the output terminal S _CLK, whether the bit 4 is used as input and output ports (P ₃₎
Or S _RDY output select bits, bits 5 to select whether to use the S _RDY / CS terminal transfers data from the least significant bit (LSB first), the transfer direction for selecting whether to perform the most significant bit (MSB first) The selection bit, bit 6, is a synchronous clock selection bit for selecting whether to use an internal clock or an external clock as the synchronous clock.

FIG. 3 is a bit configuration diagram of the serial I / O automatic transfer control register 7. Bit 0 is an automatic transfer control bit that selects whether to use serial I / O 1 in normal mode or automatic transfer mode. This bit also switches the interrupt factor. In normal mode, serial transfer is performed. A serial I / O 1 interrupt is generated every time
In automatic transfer mode, serial I / O after automatic transfer ends
Automatic transfer interrupt occurs.

[0009] Bit 1 is an automatic transfer start bit for setting the start and end of automatic transfer, and bit 2 is a transfer mode switching for selecting between a transmission-only mode and a full-duplex (transmission / reception) mode during automatic transfer. Is a bit. In the transmission-only mode, the data in the SI / O automatic transfer RAM 14 is serial
Transfer to I / O 1 and full duplex mode exchanges data in SI / O automatic transfer RAM 14 with serial I / O 1. Therefore, in the transmission only mode, the contents of the SI / O automatic transfer RAM 14 are preserved,
In the full-duplex mode, the contents of the SI / O automatic transfer RAM 14 are not saved. Bit 3 is the time of the internal clock selection, a synchronization clock output pin select bits for selecting whether to output the one clock output terminal S _CLK12 outputs a synchronous clock from the clock output terminal S _CLK11.

In the serial input / output control circuit having the above-described control register having the bit configuration, when the internal clock is selected as the transfer clock in the automatic transfer mode (full-duplex), the serial output terminal of the transfer clock is used as the serial output terminal.
_In addition to setting bit 3 of the serial I / O automatic transfer control register 7 to select either _CLK11 or _SCLK12 , set bit 3 or bit 6 of the serial I / O 1 control register 61 to either There is a need. At this time, the terminal that is not selected has high impedance.

When the external clock is selected, the internal clock is invalidated. Therefore, to activate the serial output terminal S _OUT in the full-duplex automatic transfer mode for exchanging data, the terminal 113 must be connected to the CS signal input terminal. Select and externally control the serial output terminal S _OUT and the internal clock. That is, when the CS input is “L”, S _OUT becomes active and the transfer clock (internal clock) is enabled. When the CS input is “H”, S _OUT becomes high impedance and the internal clock becomes Becomes "H".

[0010]

As described above, in the conventional input / output control circuit, the control register is used to select the serial output terminal of the transfer clock in the full-duplex automatic transfer mode.
Two bits of bit 3 and bit 6 of 61 are required, and two bits of bit 3 and bit 4 of the control register 61 are required to activate the serial output terminal S _OUT .

Generally, an IC circuit used for a control register has 8 bits, but in a conventional control register, a limited number of bits are uneconomically assigned to bits.
Therefore, in order to add a new function such as sharing an input terminal and an output terminal for effective use of the terminal, the number of control registers must be increased, and the circuit becomes large and expensive. Become.

The present invention has been made in order to solve such a problem, and it is possible to add a new function without increasing the number of control registers by optimizing the bit configuration of the control registers. And an input / output control circuit.

[0013]

According to the present invention, there is provided an input / output control circuit comprising: a first bit for setting a synchronous clock oscillation frequency when an internal clock is selected; A second bit for selecting whether to use as a terminal, a third bit for selecting an output format of an internal clock output terminal and an output terminal, a fourth bit for selecting a data transfer direction, an input / output port or an external clock input. A control register having a fifth bit for selecting whether to use it as a terminal or an internal clock output terminal, and a sixth bit for selecting whether to make the output terminal active or high impedance, / Selection of external clock and input / output port / serial input / output terminal is assigned to the same fifth bit, and only the sixth bit is used. Optimize the bit configuration of the control register as the bit configuration that activates the output terminal, assign the function to select the output format of the output terminal to the third bit, and select whether to activate the output terminal or set it to high impedance The output terminal and the input terminal can be shared by the sixth bit.

[0014]

The input / output control circuit according to the present invention sets the synchronous clock oscillation frequency when the internal clock is selected by the first bit of the control register, and uses the terminal of the input / output circuit as the input / output port with the second bit. Or the output terminal is used as the output terminal. The third bit selects whether the output format of the internal clock output terminal and the output terminal is set to, for example, three-state or open drain. The transfer direction is selected, the fifth bit selects whether to use as an input / output port or an external clock input terminal or the internal clock output terminal, and the sixth bit activates the output terminal or sets it to high impedance. Choose what to do. Therefore, while the output terminal is activated by the sixth bit to enable data output, the output is made high impedance to disable output, and data is input from this output terminal.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing the embodiments. Figure 11 shows an 8-bit clock synchronous serial
FIG. 2 is a block diagram showing a configuration of a serial I / O control circuit according to the present invention in which two I / Os are incorporated. In the figure, reference numeral 1 denotes a serial I / O which has a normal transfer function and an automatic transfer function and is used by switching between the two. Reference numeral 2 denotes a serial I / O having only the normal transfer function.

Input / output terminals 110, 11 of serial I / Os 1, 2
1, 112, 113, 214, 215, and 216 are shared with input / output ports, and it is determined whether to use them as input / output ports or serial input / output terminals by using serial I / O
It is selected by the bit values of the control register 81 and the serial I / O2 control register 82.

The serial I / O 1 has an automatic transfer mode
32-byte SI / O automatic transfer RAM 14, SI / O automatic transfer data pointer 15, serial I / O automatic transfer controllers 16 and 5
Automatic transfer interval register 17 consisting of a bit counter
Is connected.

FIG. 12 is a diagram showing the bit configuration of each of the serial I / O 1 control register 81 and the serial I / O 2 control register 82. Taking the bit configuration of the serial I / O 1 control register 81 shown in FIG.
1 and 2 are internal synchronous clock selection bits for selecting a synchronous clock oscillation frequency when an internal clock is selected, and bit 3 is used as an input / output port (P ₁ ) or a serial output terminal.
S _OUT pin select bit, bit 4 is Pch output disable bit output format of the internal clock output terminal S _CLK and a serial output terminal S _OUT to select whether CMOS3 states or N-channel open-drain select whether to use as S _OUT, Bit 5 is the least significant bit (bit 0) for data transfer
Or carried from (LSB first) or forward direction select bit for selecting the most significant bit or done from (bit 7) (MSB first), as do S _CLK output bit 6 is used as an input port or S _CLK input terminal An S _CLK terminal selection bit for selecting whether to use the S _OUT terminal, bit 7 is an S _OUT terminal control bit for selecting whether to activate or high impedance the S _OUT terminal.

FIG. 13 is a diagram showing a bit configuration of the serial I / O automatic transfer control register 9;
An automatic transfer control bit for selecting whether to use I / O 1 in normal mode or automatic transfer mode, bit 1 is an automatic transfer start bit for setting the start and end of automatic transfer, and bit 2 is for automatic transfer. , A transfer mode switching bit for selecting between the transmission only mode and the full-duplex mode, and bit 3 outputs a synchronous clock from the clock output terminal S _CLK11 or S _CLK12 when the internal clock is selected. Bit 4 is a CS terminal selection bit for selecting whether to enable or disable the CS terminal input.

The serial according to the present invention having the above configuration
The operation of the serial I / O 1 in the normal mode in the I / O control circuit will be described. 4 and 5 are diagrams showing the operation timing of the serial I / O shift register 13 during transmission and reception in the normal mode, and FIG. 6 is a timing diagram showing the operation timing of the serial I / O in the normal mode. It is a chart.

When data is written to the serial I / O shift register 13, the serial I / O counter
12 is set to "7", and the transfer clock is forced to "H". After the write cycle, every time the transfer clock changes from “H” to “L” during transmission, S _OUT
At the same time data is output from the terminal, the contents of the serial I / O shift register 13 are shifted by one bit. During reception, every time the transfer clock changes from "L" to "H", data is fetched from the _SIN terminal and the contents of the serial I / O shift register 13 are shifted by one bit.

When the internal clock is selected as the clock source, when the transfer clock (internal clock) is counted eight times, the serial I / O counter 12 becomes "0", the transfer clock stops at "H", and the serial I / O counter 12 stops. / O 1 interrupt request bit is set. After data transfer is completed, the _SOUT pin goes into a high impedance state.

On the other hand, when the external clock is selected as the clock source, the serial I / O1 interrupt request bit is set when the transfer clock is counted eight times, but the serial I / O shift is performed while the transfer clock is being input. The contents of register 13 continue to shift. The _SOUT pin does not go into the high-impedance state even after the end of data transfer. The operation of the serial I / O 2 in the normal mode is the same as the operation of the serial I / O 1.

Next, the automatic transfer mode (full duplex) of the serial I / O 1 will be described. FIG. 7 is a timing chart showing the operation timing during automatic transfer (internal clock selection). When the value n is written in the automatic transfer interval register 17, a transfer interval Ti = (n + 2) × Tc [Tc = 1 transfer clock length for one bit] at the time of automatic transfer occurs. However, the setting of the transfer interval is effective only when the internal clock is selected as the clock source.

The SI / O automatic transfer RAM 14 stores "0100 to 011
"F", and the value indicated by the SI / O automatic transfer data pointer 15 composed of a 5-bit register is set to "010".
The value obtained by adding “0” indicates the real address of the SI / O automatic transfer RAM 14.

Automatic transfer data Serial I / O Automatic transfer RA
When storing in M14, the last transfer data is the first “0100”
The storage address of the first transfer data is set to the address “0100+ (the number of transfer data bytes−1)” so as to be stored at the address. Therefore, the value of (the number of transfer data bytes-1) is set in the SI / O automatic transfer data pointer 15. When the transfer clock speed is set in bits 0, 1, and 2 of the serial I / O1 control register 81 and the automatic transfer interval is set in the automatic transfer interval register 17, the timing of automatic transfer is determined.

Writing "1" to bit 0 of the serial I / O automatic transfer control register 9 switches to the automatic transfer mode, and writing "1" to bit 1 starts automatic transfer. Bit 1 of the serial I / O automatic transfer control register 9 is always "1" during automatic transfer, and the automatic transfer can be terminated by writing "0".

When the automatic transfer starts, first, the data in the SI / O automatic transfer RAM 14 at the address designated by the SI / O automatic transfer data pointer 15 is transferred to the serial I / O shift register 13.
Is forwarded to At this time, the serial I / O counter 12 is set to "7", and the transfer clock is forced to "H". Every time the 1-bit data transfer cycle from the SI / O automatic transfer RAM 14 to the serial I / O shift register 13 is completed and the transfer clock changes from “H” to “L”, data is output from the S _OUT terminal. You. _{Each time the} transfer clock changes from "L" to "H" from the _SIN terminal, data is fetched and the content of the serial I / O shift register 13 is set to 1 at the same time.
Bit shifted. Figure 8 shows the automatic transfer mode (full duplex)
5 is a diagram showing the operation timing of the serial I / O shift register 13 in FIG.

When the transfer clock is counted eight times, the serial I / O counter 12 becomes "0", the transfer clock stops at "H", and the serial I / O shift register 13
Is transferred to the SI / O automatic transfer RAM 14 at the address indicated by the SI / O automatic transfer data pointer 15. Next, the contents of the SI / O automatic transfer data pointer 15 are decremented by (-1), and the SI / O automatic transfer RAM 14 at the address indicated by the SI / O automatic transfer data pointer 15 is read.
Is transferred to the serial I / O shift register 13.
After the transfer interval Ti set by the automatic transfer interval register 17 has elapsed, the transfer clock is output, and the serial transfer is restarted (when the internal clock is selected). When the external clock is selected, the setting of the automatic transfer interval register 17 becomes invalid, so that it is necessary to control the transfer clock externally.

When the content of the SI / O automatic transfer data pointer 15 becomes "0", the serial transfer ends. Serial I / O
After the data in the shift register 13 has been transferred to the SI / O automatic transfer RAM 14, the serial I / O automatic transfer interrupt request bit is set, and bit 1 of the serial I / O automatic transfer control register 9 is cleared to perform automatic transfer. Ends.

The operation in the transmission-only mode is the same as that in the full-duplex mode except that data is not transferred from the serial I / O shift register 13 to the SI / O automatic transfer RAM 14.

FIG. 9 is a timing chart when the clock output terminals S _CLK11 and S _CLK12 are switched and used in the automatic transfer mode. When the internal clock is selected, bit 3 of the serial I / O automatic transfer control register 9 is set to "1".
When set to, the synchronous clock serial output terminal S
_CLK12 is selected. At this time, the P ₂ / S _CLK11 terminal 112 becomes high impedance. Connect terminals 112 and 113 to S
_To select the clock output terminals of _CLK11 and _SCLK12 , only bit 6 of the serial I / _O1 control register 81 needs to be set.

When the external clock is selected, the setting of the internal clock and the transfer interval in the automatic transfer interval register 17 becomes invalid, but bit 7 of the serial I / O1 control register 81
Is activated, and bit 4 of the serial I / O automatic transfer control register 9 is set to “1” to enable the CS signal input. When the CS input is “L”, the transfer clock (internal clock) is enabled, and the CS input is “H”.
In this case, the internal clock becomes "H".

FIG. 10 is a timing chart of the automatic transfer mode when an external clock is selected. When the CS input is not used, or when CS is “L”, the external clock must be controlled because the data in the serial I / O shift register 13 continues to be shifted while the transfer clock is input even after the end of automatic transfer. There is.

As described above, the serial I / O according to the present invention
In the serial I / O control register of the control circuit, the output terminal S _CLK11 or S _CLK12 of the internal clock, which had to set both bit 3 and bit 6 in the past, can be selected by setting only bit 6. Good. Internal clock /
The selection of the external clock and the input / output port / input / output terminal is assigned to the same bit (bit 6), and optimization is achieved.

Also, by optimizing the bit assignment of the serial I / O control register, the serial output terminal S
A function (bit 4) for selecting the output format of the _CLK and S _OUT terminals to be CMOS or N-channel open drain is added.

Further, since the active / high impedance of the S _OUT terminal can be set only by bit 3,
In addition to the effective bit allocation, it is possible to select whether one terminal is used as an input terminal or an output terminal by bit 3, and the input / output terminals can be shared.

FIGS. 14 and 15 are circuit diagrams showing an example of a control signal generating circuit for each port of the single-chip microcontroller according to the present invention having the serial I / Os 1 and 2 built therein.

FIG. 16 is a circuit diagram showing an example of a control signal generation circuit for each port of a circuit in which the terminal 214 of the serial I / O 2 is used as an input / output terminal.

In the figures, SM10, SM11, SM12, SM13, SM
14, SM15, SM16 and SM17 are the signals of bits 0, 1, 2, 3, 4, 5, 6 and 7 of the serial I / O 1 control circuit 81, respectively, and SM20, SM21, SM22, SM23, SM24, SM25 , SM26 and SM
27 are bits 0, 1, and 1 of the serial I / O 2 control circuit 82, respectively.
2, 3, 4, 5, 6 and 7 signals, plus SIO1AM0, SAM0,
SAM1, SAM2, SAM3 and SAM4 indicate the signals of bits 0, 1, 2, 3 and 4 of the serial I / O automatic transfer control register 9.

[0041]

As described above, the input / output control circuit of the present invention optimizes the bit allocation of the control register, thereby enabling the selection of the output format of the output terminal and the output terminal selection function without increasing the number of control registers. This provides an excellent effect that an active / high impedance setting function is added and that the input terminal and the output terminal can be shared by setting the active / high impedance of the output terminal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of two serial I / Os built in a conventional serial I / O control circuit.

FIG. 2 is a diagram showing a bit configuration of a serial I / O control register incorporated in a conventional serial I / O control circuit.

FIG. 3 is a diagram showing a bit configuration of a serial I / O automatic transfer control register built in a conventional serial I / O control circuit.

FIG. 4 is a diagram showing operation timing of a serial I / O shift register in a normal mode (transmission).

FIG. 5 is a diagram showing operation timing of a serial I / O shift register in a normal mode (reception).

FIG. 6 is a timing chart showing the operation timing of serial I / O in a normal mode.

FIG. 7 is a timing chart showing the operation timing of serial I / O in the automatic transfer mode (internal clock selection).

FIG. 8: Serial I / O in automatic transfer mode (full duplex)
FIG. 6 is a diagram illustrating operation timing of an O register.

FIG. 9 is a timing chart showing the operation timing of the serial I / O when the clock output terminal is switched and used.

FIG. 10 is a timing chart showing the operation timing of serial I / O in the automatic transfer mode (external clock selection).

FIG. 11 is a block diagram showing a configuration of two serial I / Os built in a serial I / O control circuit according to the present invention.

FIG. 12 is a diagram showing a bit configuration of a serial I / O control register incorporated in the serial I / O control circuit according to the present invention.

FIG. 13 is a diagram showing a bit configuration of a serial I / O automatic transfer control register built in a serial I / O control circuit according to the present invention.

FIG. 14 is a circuit diagram showing a configuration of a control signal generation circuit for a terminal of a serial I / O 1 in a single-chip microcontroller according to the present invention.

FIG. 15 is a circuit diagram showing a configuration of a control signal generation circuit for a terminal of a serial I / O 2 in a single-chip microcontroller according to the present invention.

FIG. 16 is a circuit diagram showing a configuration of a terminal control signal generation circuit in input / output terminal sharing in the single-chip microcontroller according to the present invention.

[Explanation of symbols]

 1, 2 serial I / O 12 serial I / O counter 13 serial I / O shift register 81 serial I / O 1 control register 82 serial I / O 2 control register 9 serial I / O automatic transfer control register

Claims (2)

(57) [Claims] An input / output state of an input / output circuit in which data is transferred via a bidirectional bus in synchronization with an internal clock or an external clock and the data transfer direction is reversible is set by a value of each bit of a control register. A first bit for setting a synchronous clock oscillation frequency when an internal clock is selected, and a second bit for selecting whether to use a terminal of the input / output circuit as an input / output port or an output terminal A third bit for selecting the output format of the internal clock output terminal and the output terminal, a fourth bit for selecting the data transfer direction, used as an input / output port or an external clock input terminal, or used as an internal clock output terminal. And a sixth bit for selecting whether to make the output terminal active or high impedance. An input / output control circuit comprising a control register. 2. A single-chip microcontroller comprising the input / output control circuit according to claim 1.