JPH05143509A - Input and output control circuit - Google Patents

Abstract

PURPOSE:To increase functions without increasing the number of control registers by optimizing bit structure. CONSTITUTION:The bit allocation of the serial I/O control registers 81 and 82 is optimized, the selection of external/internal clocks and an input and output port/serial input and output terminal are switched by same bit (bit 6) and the active/high-impedance of the serial output terminal SOUT can be set by one bit (bit 7). Therefore, the one terminal is switched into an output or input by setting the output to be active or high-impedance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output control circuit for selecting an input / output state of an input / output circuit which shares its terminal with an input / output port by each bit value of a control register.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram showing the configuration of a conventional serial I / O control circuit incorporating two 8-bit clock synchronous serial I / O. In the figure, reference numeral 1 is a serial I / O that has a normal transfer function and an automatic transfer function built in and is used by switching between the two. Reference numeral 2 is a serial I / O having only the normal transfer function.

Input / output terminals 110, 11 of serial I / O 1, 2
1, 112, 113, 214, 215, and 216 are also used as input / output ports, and whether they are used as input / output ports or as serial input / output terminals will be described later in Serial I / O 1
It is selected by each bit value of the control register 61 and the serial I / O 2 control register 62.

The serial I / O 1 includes a 32-byte SI / O automatic transfer RAM 14, an SI / O automatic transfer data pointer 15, a serial I / O automatic transfer controller 16 and a 5-bit counter for the automatic transfer mode. The configured automatic transfer interval register 17 is connected.

FIG. 2 is a diagram showing respective bit configurations of the serial I / O 1 control register 61 and the serial I / O 2 control register 62. Taking the bit configuration of the serial I / O 1 control register 61 shown in FIG. 2 (a) as an example, bit 0,
1 and 2 are internal synchronous clock selection bits that set the synchronous clock oscillation frequency when the internal clock is selected, and bit 3 is used as an input / output port (P ₁ , P ₂ , P ₃ ) or serial output terminal S _OUT or clock input. serial I / O 1 port selection bits for selecting whether to use as the output terminal S _CLK, whether the bit 4 is used as input and output ports (P ₃₎
Or S _RDY output select bits, bits 5 to select whether to use the S _RDY / CS terminal transfers data from the least significant bit (LSB first), the transfer direction for selecting whether to perform the most significant bit (MSB first) The selection bit, bit 6, is a synchronous clock selection bit for selecting whether to use the internal clock or the external clock as the synchronous clock.

FIG. 3 is a bit configuration diagram of the serial I / O automatic transfer control register 7. Bit 0 is an automatic transfer control bit that selects whether serial I / O 1 is used in normal mode or automatic transfer mode. This bit also switches interrupt factors. In normal mode, serial transfer is performed. A serial I / O 1 interrupt is generated at each end,
In the automatic transfer mode, serial I / O after completion of automatic transfer
An automatic transfer interrupt occurs.

Bit 1 is an automatic transfer start bit that sets the start and end of automatic transfer, and bit 2 is a transfer mode switch that selects a transmission-only mode or full-duplex (transmission / reception) mode during automatic transfer. Is a bit. In the transmission-only mode, the data in the SI / O automatic transfer RAM 14 is serialized.
Transfer to I / O 1, full-duplex mode swaps data in SI / O automatic transfer RAM 14 with serial I / O 1. Therefore, the contents of the SI / O automatic transfer RAM 14 are saved in the send-only mode,
The contents of SI / O automatic transfer RAM 14 are not saved in full-duplex mode. Bit 3 is a synchronous clock output terminal selection bit for selecting whether to output the synchronous clock from the clock output terminal S _CLK11 or the clock output terminal S _CLK12 when the internal clock is selected.

In the serial input / output control circuit having the control register having the bit configuration as described above, when the internal clock is selected as the transfer clock in the automatic transfer mode (full-duplex), S is used as the serial output terminal of the transfer clock.
_In addition to setting bit 3 of serial I / O automatic transfer control register 7 to select either _CLK11 or S _CLK12 , set bit 3 or bit 6 of serial I / O 1 control register 61 to either There is a need. At this time, the terminal not selected becomes high impedance.

Since the internal clock is invalid when the external clock is selected, in order to activate the serial output terminal S _OUT in the full-duplex automatic transfer mode for exchanging data, the terminal 113 is used as the CS signal input terminal. Select to control the serial output pin S _OUT and the internal clock externally. That is, when the CS input is "L", S _OUT becomes active and the transfer clock (internal clock) is enabled, and when the CS input is "H", S _OUT becomes high impedance and the internal clock is Becomes "H".

[0010]

As described above, in the conventional input / output control circuit, the control register is used to select the serial output terminal of the transfer clock in the full-duplex automatic transfer mode.
Two bits, bit 3 and bit 6, of 61 are required, and two bits, bit 3 and bit 4, of control register 61 are required to activate the serial output terminal S _OUT .

Generally, the IC circuit used for the control register has 8 bits, but in the conventional control register, uneconomical bit allocation is made to a limited number of bits.
Therefore, the number of control registers must be increased in order to add a new function such as sharing an input terminal and an output terminal in order to effectively use the terminals, and the circuit becomes large and expensive. Become.

The present invention has been made to solve such a problem, and by optimizing the bit configuration of the control register, a new function can be added without increasing the number of control registers. The purpose of the present invention is to provide an input / output control circuit.

[0013]

An input / output control circuit according to the present invention uses a first bit for setting a synchronous clock oscillation frequency when an internal clock is selected, a terminal of the input / output circuit as an input / output port, or an output. A second bit for selecting whether to use as a terminal, a third bit for selecting the output format of the internal clock output terminal and the output terminal, a fourth bit for selecting the data transfer direction, an input / output port or an external clock input The internal clock is provided with a control register having a fifth bit for selecting whether to use it as a terminal or an internal clock output terminal, and a sixth bit for selecting whether to make the output terminal active or high impedance. / External clock and input / output port / Serial input / output pin selection is assigned to the same 5th bit, and only 6th bit Optimize the bit configuration of the control register as the bit configuration that activates the output terminal, assign the function to select the output format of the output terminal to the third bit, and select whether to activate the output terminal or set it to high impedance. It is characterized in that the output terminal and the input terminal can be shared by the sixth bit.

[0014]

In the input / output control circuit according to the present invention, the first bit of the control register sets the synchronous clock oscillation frequency when the internal clock is selected, and the second bit uses the terminal of the input / output circuit as the input / output port. The output format of the internal clock output terminal and the output terminal, for example, 3 states or open drain is selected by the third bit, and the fourth bit of the data is selected. Select the transfer direction, select the 5th bit to use as an I / O port or external clock input terminal or the internal clock output terminal, and select the 6th bit to activate the output terminal or set it to high impedance. Select whether to do. Therefore, the sixth bit activates the output terminal to enable data output, while the high-impedance state disables output, and data is input from this output terminal.

[0015]

The present invention will be described below with reference to the drawings showing the embodiments thereof. Figure 11 shows 8-bit clock synchronous serial
FIG. 3 is a block diagram showing a configuration of a serial I / O control circuit according to the present invention, which has two I / Os built therein. In the figure, reference numeral 1 is a built-in normal transfer function and automatic transfer function, two serial I / Os are used by switching them, and 2 is a serial I / O having only a normal transfer function.

Input / output terminals 110, 11 of serial I / O 1, 2
1, 112, 113, 214, 215, and 216 are also used as input / output ports, and whether they are used as input / output ports or as serial input / output terminals will be described later in Serial I / O 1
It is selected by the bit value of the control register 81 and the serial I / O 2 control register 82.

Serial I / O 1 is for automatic transfer mode.
32-byte automatic SI / O transfer RAM 14, SI / O automatic transfer data pointer 15, serial I / O automatic transfer controller 16 and 5
Automatic transfer interval register 17 consisting of bit counter
Are connected.

FIG. 12 is a diagram showing the bit configuration of each of the serial I / O 1 control register 81 and the serial I / O 2 control register 82. The bit configuration of the serial I / O 1 control register 81 shown in FIG.
1 and 2 are internal synchronous clock selection bits that select the synchronous clock oscillation frequency when the internal clock is selected, and bit 3 is used as an input / output port (P ₁ ) or serial output pin
S _OUT pin select bit, bit 4 is Pch output disable bit output format of the internal clock output terminal S _CLK and a serial output terminal S _OUT to select whether CMOS3 states or N-channel open-drain select whether to use as S _OUT, Bit 5 is the least significant bit (bit 0) for data transfer
Transfer direction selection bit that selects whether to perform from (LSB first) or most significant bit (bit 7) (MSB first), bit 6 is used as an I / O port or S _CLK input pin, or as an S _CLK output pin The S _CLK pin select bit that selects whether to use it, bit 7 is the S _OUT pin control bit that selects whether the S _OUT pin is active or in high impedance.

FIG. 13 is a diagram showing the bit configuration of the serial I / O automatic transfer control register 9, where bit 0 is the serial
An automatic transfer control bit that selects whether I / O 1 is used in normal mode or automatic transfer mode, bit 1 is an automatic transfer start bit that sets the start and end of automatic transfer, and bit 2 is used during automatic transfer. , Transfer mode switching bit that selects transmission-only mode or full-duplex mode. Bit 3 outputs synchronous clock from clock output pin S _CLK11 or clock output pin S _CLK12 when internal clock is selected. Synchronous clock output terminal selection bit for selecting whether to perform, and bit 4 is a CS terminal selection bit for selecting whether to enable or disable the CS terminal input.

The serial according to the present invention having the above structure
The operation of the serial I / O 1 in the normal mode in the I / O control circuit will be described. 4 and 5 are diagrams showing the operation timing of the serial I / O shift register 13 at the time of transmission and reception in the normal mode, and FIG. 6 is a timing showing the operation timing of the serial I / O at the normal mode. It is a chart.

When the serial I / O shift register 13 is written, the serial I / O counter is written during the write cycle.
12 is set to "7" and the transfer clock is forced to "H". After the write cycle, at the time of transmission, S _OUT is output every time the transfer clock changes from “H” to “L”.
At the same time as the data is output from the terminal, the contents of the serial I / O shift register 13 are shifted by 1 bit. Further, at the time of reception, each time the transfer clock changes from "L" to "H", data is taken in from the S _IN terminal and at the same time, the content of the serial I / O shift register 13 is shifted by 1 bit.

When the internal clock is selected as the clock source, the serial I / O counter 12 becomes "0" when the transfer clock (internal clock) is counted 8 times, the transfer clock stops in the "H" state, and the serial I / O counter 12 stops. / O 1 interrupt request bit is set. After data transfer is completed, the S _OUT pin goes into a high impedance state.

On the other hand, when the external clock is selected as the clock source, the serial I / O 1 interrupt request bit is set when the transfer clock is counted 8 times, but the serial I / O shift is performed while the transfer clock is being input. The contents of register 13 continue to be shifted. In addition, the S _OUT pin does not enter the high impedance state even after the data transfer is completed. The operation of the serial I / O 2 in the normal mode is the same as the operation of the serial I / O 1.

Next, the automatic transfer mode (full duplex) of the serial I / O 1 will be described. FIG. 7 is a timing chart showing the operation timing during automatic transfer (internal clock selection). When the value n is written in the automatic transfer interval register 17, the transfer interval Ti = (n + 2) × Tc [Tc = 1 transfer clock length for one bit] during automatic transfer is generated. However, this transfer interval setting is valid only when the internal clock is selected as the clock source.

The SI / O automatic transfer RAM 14 is "0100 to 011".
"010" is assigned to the value indicated by SI / O automatic transfer data pointer 15 which is assigned to address "F" and consists of a 5-bit register.
The value with "0" added indicates the real address of the SI / O automatic transfer RAM 14.

Automatic transfer data to serial I / O Automatic transfer RA
When stored in M 14, the last transfer data is the first "0100"
The storage address of the first transfer data is set to the address “0100+ (the number of transfer data bytes-1)” so that it is stored in the address. Therefore, the value of (the number of transfer data bytes-1) is set in the SI / O automatic transfer data pointer 15. When the transfer clock speed is set in bits 0, 1 and 2 of the serial I / O 1 control register 81 and the automatic transfer interval is set in the automatic transfer interval register 17, the automatic transfer timing is determined.

Writing "1" to bit 0 of the serial I / O automatic transfer control register 9 enters the automatic transfer mode, and writing "1" to bit 1 starts automatic transfer. Bit 1 of the serial I / O automatic transfer control register 9 is always "1" during automatic transfer, and automatic transfer can be ended by writing "0".

When the automatic transfer is started, first, the data in the SI / O automatic transfer RAM 14 at the address designated by the SI / O automatic transfer data pointer 15 is transferred to the serial I / O shift register 13
Transferred to. At this time, the serial I / O counter 12 is set to "7" and the transfer clock is forced to "H". Data is output from the S _OUT pin every time the 1-bit data transfer cycle from the SI / O automatic transfer RAM 14 to the serial I / O shift register 13 is completed and the transfer clock changes from “H” to “L”. It Data is taken in from the S _IN terminal every time the transfer clock changes from “L” to “H”, and at the same time, the content of the serial I / O shift register 13 becomes 1
Bit-shifted. Figure 8 shows automatic transfer mode (full duplex)
6 is a diagram showing an operation timing of the serial I / O shift register 13 in FIG.

When the transfer clock is counted eight times, the serial I / O counter 12 becomes "0", the transfer clock stops in the "H" state, and the serial I / O shift register 13
Is transferred to the SI / O automatic transfer RAM 14 at the address indicated by the SI / O automatic transfer data pointer 15. Next, the content of the SI / O automatic transfer data pointer 15 is decremented by (-1), and the SI / O automatic transfer RAM 14 at the address indicated by the SI / O automatic transfer data pointer 15
Is transferred to the serial I / O shift register 13.
After the transfer interval Ti set by the automatic transfer interval register 17 has elapsed, the transfer clock is output and the serial transfer is restarted (when the internal clock is selected). Since the setting of the automatic transfer interval register 17 is invalid when the external clock is selected, it is necessary to control the transfer clock externally.

When the content of the SI / O automatic transfer data pointer 15 becomes "0", the serial transfer ends. Serial I / O
After the data in the shift register 13 is transferred to the SI / O automatic transfer RAM 14, the serial I / O automatic transfer interrupt request bit is set, and bit 1 of the serial I / O automatic transfer control register 9 is cleared to automatically transfer the data. Ends.

The operation in the transmission-only mode is the same as that in the full-duplex mode except that data is not transferred from the serial I / O shift register 13 to the SI / O automatic transfer RAM 14.

FIG. 9 is a timing chart when the clock output terminals S _CLK11 and S _CLK12 are switched and used in the automatic transfer mode. When the internal clock is selected, set bit 3 of serial I / O automatic transfer control register 9 to "1".
When set to, the synchronous clock serial output pin S
_CLK12 is selected. At this time, the P ₂ / S _CLK11 terminal 112 becomes high impedance. Connect terminals 112 and 113 to S
_To select as the clock output terminal of _CLK11 and S _CLK12 , only bit 6 of the serial I / O 1 control register 81 needs to be set.

When the external clock is selected, the internal clock and the transfer interval setting in the automatic transfer interval register 17 are invalid, but bit 7 of the serial I / O 1 control register 81 is disabled.
Is activated, and bit 4 of the serial I / O automatic transfer control register 9 is set to "1" to enable the CS signal input. When CS input is “L”, transfer clock (internal clock) is enabled and CS input is “H”
In this case, the internal clock becomes "H".

FIG. 10 is a timing chart of the automatic transfer mode when the external clock is selected. When CS input is not used, or when CS is "L", the data in the serial I / O shift register 13 continues to be shifted while the transfer clock is being input even after the end of automatic transfer, so it is necessary to control the external clock. There is.

As described above, the serial I / O according to the present invention
In the serial I / O control register of the control circuit, only bit 6 can be selected for the internal clock output terminal S _CLK11 or S _CLK12 , which conventionally had to set both bit 3 and bit 6. Good. Further internal clock /
The selection of the external clock and the input / output port / input / output terminal is assigned to the same bit (bit 6) for optimization.

Further, by optimizing the bit allocation of the serial I / O control register, the serial output terminal S
A function (bit 4) to select the output format of the _CLK and S _OUT terminals to CMOS or N channel open drain is added.

Furthermore, since the active / high impedance of the S _OUT terminal can be set only by bit 3,
In addition to effective bit allocation, it is possible to select whether one terminal is used as an input terminal or an output terminal by means of bit 3 so that input / output terminals can be shared.

FIGS. 14 and 15 are circuit diagrams showing an example of a control signal generating circuit for each port of the single-chip microcontroller according to the present invention which incorporates the serial I / Os 1 and 2.

FIG. 16 is a circuit diagram showing an example of a control signal generation circuit for each port of the circuit in which the terminal 214 of the serial I / O 2 is used as an input / output terminal.

In the figure, SM10, SM11, SM12, SM13, SM
14, SM15, SM16 and SM17 are signals of bits 0, 1, 2, 3, 4, 5, 6 and 7 of the serial I / O 1 control circuit 81, and SM20, SM21, SM22, SM23, SM24, SM25. , SM26 and SM
27 are bits 0, 1, and 1 of the serial I / O 2 control circuit 82, respectively.
Signals of 2, 3, 4, 5, 6 and 7, as well as SIO1AM0, SAM0,
SAM1, SAM2, SAM3 and SAM4 indicate signals of bits 0, 1, 2, 3 and 4 of the serial I / O automatic transfer control register 9.

[0041]

As described above, the input / output control circuit of the present invention optimizes the bit allocation of the control register, thereby selecting the output format of the output terminal and the output terminal selection function without increasing the number of control registers. The active / high-impedance setting function is added, and the active / high-impedance setting of the output terminal allows the input terminal and the output terminal to be commonly used.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of two serial I / Os incorporated in a conventional serial I / O control circuit.

FIG. 2 is a diagram showing a bit configuration of a serial I / O control register incorporated in a conventional serial I / O control circuit.

FIG. 3 is a diagram showing a bit configuration of a serial I / O automatic transfer control register incorporated in a conventional serial I / O control circuit.

FIG. 4 is a diagram showing operation timings of a serial I / O shift register in a normal mode (transmission).

FIG. 5 is a diagram showing an operation timing of a serial I / O shift register in a normal mode (reception).

FIG. 6 is a timing chart showing the operation timing of serial I / O in the normal mode.

FIG. 7 is a timing chart showing the operation timing of serial I / O in the automatic transfer mode (internal clock selection).

[Figure 8] Serial I / O in automatic transfer mode (full duplex)
It is a figure which shows the operation timing of an O register.

FIG. 9 is a timing chart showing the operation timing of serial I / O when the clock output terminals are switched and used.

FIG. 10 is a timing chart showing the operation timing of serial I / O in the automatic transfer mode (external clock selection).

FIG. 11 is a block diagram showing a configuration of two serial I / Os incorporated in a serial I / O control circuit according to the present invention.

FIG. 12 is a diagram showing a bit configuration of a serial I / O control register incorporated in a serial I / O control circuit according to the present invention.

FIG. 13 is a diagram showing a bit configuration of a serial I / O automatic transfer control register incorporated in a serial I / O control circuit according to the present invention.

FIG. 14 is a circuit diagram showing a configuration of a control signal generation circuit of a terminal of the serial I / O 1 in the single-chip microcontroller according to the present invention.

FIG. 15 is a circuit diagram showing a configuration of a control signal generation circuit for a terminal of serial I / O 2 in the single-chip microcontroller according to the present invention.

FIG. 16 is a circuit diagram showing a configuration of a terminal control signal generation circuit in the case of sharing an input terminal / output terminal in the single-chip microcontroller according to the present invention.

[Explanation of symbols]

 1, 2 Serial I / O 12 Serial I / O counter 13 Serial I / O shift register 81 Serial I / O 1 control register 82 Serial I / O 2 control register 9 Serial I / O automatic transfer control register

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[Procedure amendment]

[Submission date] March 3, 1992

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

[Fig. 2]

[Procedure 3]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 11

[Correction method] Change

[Correction content]

FIG. 11

Claims (2)

[Claims] 1. An input / output state of an input / output circuit in which data is transferred through a bidirectional bus in synchronization with an internal clock or an external clock and the data transfer direction is reversible is set by the value of each bit of a control register. In the input / output control circuit, the first bit that sets the synchronous clock oscillation frequency when the internal clock is selected, and the second bit that selects whether the terminal of the input / output circuit is used as the input / output port or the output terminal , Internal clock output terminal and third bit for selecting output format of output terminal, fourth bit for selecting data transfer direction, used as input / output port or external clock input terminal, or used as internal clock output terminal And a sixth bit for selecting whether to make the output terminal active or high impedance. An input / output control circuit comprising a control register for controlling the input / output. 2. A single-chip microcontroller including the input / output control circuit according to claim 1.