WO2024017337A1

WO2024017337A1 - Fifo storage control circuit and method, chip, and electronic device

Info

Publication number: WO2024017337A1
Application number: PCT/CN2023/108417
Authority: WO
Inventors: 秦晨钟; 谢韶波; 符土建; 李晓
Original assignee: 芯海科技（深圳）股份有限公司
Priority date: 2022-07-22
Filing date: 2023-07-20
Publication date: 2024-01-25
Also published as: CN117435158A

Abstract

Disclosed in the present application are a FIFO storage control circuit and method, a chip, and an electronic device. The circuit comprises: a single-port random access memory, a switching control circuit and a switching circuit, wherein a switching signal is generated by means of the switching control circuit, and the switching signal comprises a reading switching signal or a writing switching signal; according to the switching signal, the switching circuit transmits to the single-port random data memory an instruction corresponding to the switching signal, so as to execute a preset operation on the single-port random data memory according to the instruction, the instruction comprising a reading instruction or a writing instruction, and the preset operation comprising a reading operation or a writing operation.

Description

A FIFO storage control circuit, method, chip and electronic device

Cross-references to related applications

This application requests the priority of the Chinese patent application submitted to the China Patent Office on July 7, 2023, with the application number 202310836566.7 and the invention name "A FIFO storage control circuit, method, chip and electronic device". All its contents are approved by This reference is incorporated into this application.

This application claims the priority of the Chinese patent application submitted to the China Patent Office on July 22, 2022, with the application number 202210871438.1 and the invention name "A FIFO storage control circuit, method, chip and electronic device". All its contents are approved by This reference is incorporated into this application.

Technical field

The present application relates to the field of data storage technology, and more specifically, to a FIFO storage control circuit, method, chip and electronic device.

Background technique

FIFO (First Input First Output) memory is a first-in first-out cache device. Generally, FIFO memory is divided into synchronous FIFO and asynchronous FIFO. Synchronous FIFO means that the read operation clock and write operation clock are synchronous clocks; asynchronous FIFO means that the read operation clock and write operation clock are asynchronous clocks. Related technologies cannot meet asynchronous FIFO requirements when using single-port static random access memory to implement full-speed FIFO memory.

Contents of the invention

This application proposes a FIFO storage control circuit, method, chip and electronic device to improve the above problems.

In the first aspect, embodiments of the present application provide a FIFO storage control circuit, including: a single-port random data memory, a switching control circuit and a switching circuit. The switching control circuit is used to generate a switching signal, the switching signal includes a reading switching signal or a writing switching signal; the switching circuit transmits an instruction corresponding to the switching signal to the single-port randomizer according to the switching signal. data memory to randomize the single port The machine data memory performs preset operations, wherein the instructions include read instructions or write instructions, and the preset operations include read operations or write operations.

In the second aspect, embodiments of the present application provide a FIFO storage control method, including generating a switching signal according to a received communication instruction; the switching signal includes a read switching signal or a writing switching signal;

According to the switching signal, an instruction corresponding to the switching signal is transmitted to the single-port random access data memory to perform a preset operation on the single-port random access data memory, wherein the instruction includes a read instruction or a write instruction, and the Preset operations include read operations or write operations.

In a third aspect, embodiments of the present application provide a chip including the above-mentioned FIFO storage control circuit.

In a fourth aspect, embodiments of the present application provide an electronic device, including the above-mentioned FIFO storage control circuit or the above-mentioned chip.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.

Figure 1 shows a schematic structural block diagram 1 of a FIFO storage control circuit provided by this application;

Figure 2 shows a schematic structural block diagram 2 of a FIFO storage control circuit provided by this application;

Figure 3 shows an implementation block diagram of a read-priority FIFO storage control circuit provided by this application;

Figure 4 shows an implementation block diagram of a write-priority FIFO storage control circuit provided by this application;

Figure 5 shows a schematic flow chart 1 of a FIFO storage control method provided by this application;

Figure 6 shows a schematic flow chart 2 of a FIFO storage control method provided by this application;

Figure 7 shows a schematic flow chart 3 of a FIFO storage control method provided by this application;

Figure 8 shows a schematic flow chart 4 of a FIFO storage control method provided by this application;

Figure 9 shows a schematic flow chart 5 of a FIFO storage control method provided by this application;

Figure 10 shows a schematic structural diagram of a chip provided by this application;

Figure 11 shows a schematic structural diagram of an electronic device provided by this application.

In the attached figure: 100-FIFO storage control circuit; 110-single port random data memory; 120-switching control circuit; 130-switching circuit; 140-data buffer; 141-data write buffer; 142-data read buffer ; 151-data writing interface; 152-data reading interface; 160-data control circuit.

Detailed ways

The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. Down The embodiments described above with reference to the accompanying drawings are exemplary and are only used to explain the present application and cannot be understood as limiting the present application.

In order to enable those in the technical field to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only These are part of the embodiments of this application, but not all of them. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

In the embodiments of this application, at least one refers to one or more; multiple refers to two or more. In the description of this application, words such as "first", "second" and "third" are only used for the purpose of distinguishing the description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying. order.

Reference in this specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Therefore, in this specification, the terms "including", "includes", "having" and their variations all mean "including but not limited to" unless otherwise specifically emphasized.

It should be noted that “connection” in the embodiments of this application can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between two electrical components. For example, A and B may be connected directly, or A and B may be connected indirectly through one or more other electrical components.

FIFO memory is First In First Out memory, which is composed of several storage units. After data is written, it remains unchanged. The FIFO function is implemented by automatically modifying the address pointer inside the chip. FIFO is generally used for data transmission between different clock domains, and FIFO can be used as a data buffer between different clock domains. The FIFO memory can pre-write the obtained data into the FIFO buffer, and then read out the data in the order of writing to the FIFO buffer first and then outputting it first. Generally, the FIFO memory storage unit uses static random access memory (Static Random-Access Memory, SRAM).

Static random access memory is divided into single-port static random access memory, dual-port static random access memory and pseudo-dual-port static random access memory. Single-port static random access memory means that the storage unit of static random access memory contains only one set of access interfaces; dual-port static random access memory means that the storage unit of static random access memory contains two sets of access interfaces, which can independently and simultaneously access static random access memory. Random access memory data; pseudo-dual-port static random access memory means that the storage unit of static random access memory contains 2 sets of access interfaces, which can independently access static random access memory data, but cannot access it simultaneously.

Currently, FIFO memory is divided into synchronous FIFO and asynchronous FIFO. Synchronous FIFO means that the read operation clock and write operation clock are synchronous clocks; asynchronous FIFO means that the read operation clock and write operation clock are asynchronous clocks.

In current social life, the demand for asynchronous memory is also widespread, such as writing data from time to time in integrated circuits, reading data serially through communication interfaces such as SPI (Serial Peripheral Interface, Serial Peripheral Interface), or communicating with SPI etc. The interface serially writes data, the integrated circuit reads data from time to time, or the integrated circuit internally reads data from time to time, writes data from time to time, etc. In application scenarios that do not continuously read and write operations for a long time, an asynchronous storage controller is required. Perform operations.

In the design of asynchronous FIFO memory, dual-port static random access memory is commonly used as the storage unit of FIFO memory. However, the area of dual-port static random access memory is about twice the area of single-port static random access memory, which is not conducive to reducing the area of integrated circuits in practical applications. Limited practicality.

In order to solve the above existing problems, embodiments of the present application provide a FIFO storage control circuit, which includes: a single-port random data memory, a switching control circuit and a switching circuit. The switching control circuit is used to generate a switching signal, and the switching signal includes reading the switching signal or writing the switching signal; the switching circuit is used to receive the switching signal sent by the switching control circuit, and transmit the instructions corresponding to the switching signal to the single-port random data memory, The single-port random access data memory is configured to perform a preset operation corresponding to the instruction according to the instruction, wherein the instruction includes a read instruction or a write instruction, and the preset operation includes a read operation or a write operation.

By setting the single-port random data memory, the switching control circuit generates a switching signal, and the switching circuit performs preset operations on the single-port random data memory according to the instructions corresponding to the switching signal according to the switching signal sent by the switching control circuit. That is, when the switching control circuit outputs the write switching signal, the single-port random data memory can be written; only when the switching control circuit outputs the read switching signal, the single-port random data memory can be read. Using a single-port random data memory can meet the asynchronous requirements of FIFO memory, effectively reducing the area of FIFO memory and reducing costs.

The FIFO storage control circuit is described in detail below. Please refer to Figure 1. An embodiment of the present application provides a FIFO storage control circuit 100. The FIFO storage control circuit 100 includes: a single-port random data memory 110, a switching control circuit 120 and Switching circuit 130. Among them, the single-port random data memory 110 can be used to store data; the switching control circuit 120 is used to generate switching signals, which include reading switching signals or writing switching signals; the switching circuit 130 is connected to the switching control circuit 120 and the single-port random data respectively. The memory 110 is used to transmit instructions corresponding to the switching signal to the single-port random access data memory 110 according to the switching signal, so as to perform preset operations on the single-port random access data memory 110, where the instructions include read instructions or write instructions, and the preset operations include Read operation or write operation.

The single-port random access data memory 110 means that the storage unit of the random access data memory only includes one set of access interfaces. The single-port random access data memory 110 uses the same set of address lines when performing read or write operations.

In this embodiment, the read instruction includes but is not limited to read enable information and read address, and the write instruction includes but is not limited to write enable information and write address; the read operation may be to read the single-port random access data memory 110 The writing operation may be to write data to the single-port random access data memory 110 .

In some embodiments, the FIFO storage control circuit also includes a data writing interface 151 and a data reading interface 152. The switching circuit 130 is connected to the data writing interface 151 and the data reading interface 152 respectively, and is used to control data writing according to the switching signal. The connection status of the input interface 151 and the data reading interface 152 with the single-port random access data memory 110.

As an implementation manner, the switching circuit 130 is configured to receive the read switching signal sent by the switching control circuit 120 and connect the data reading interface 152 to the single-port random access data memory 110 according to the reading switching signal. The output read command executes reading on the single-port random access data memory 110 The fetch operation is to read the data stored in the single-port random access data memory 110. When the data reading interface 152 is connected to the single-port random access data memory 110, the data writing interface 151 and the single-port random access data memory 110 are in a non-conducting state. When the switching signal sent by the switching control circuit is a read switching signal, a read operation is performed on the single-port random access data memory 110. During this process, the write operation on the single-port random access data memory 110 is prohibited.

As another implementation, the switching circuit 130 is also used to receive the writing switching signal sent by the switching control circuit 120, and connect the data writing interface 151 to the single-port random data memory 110 according to the writing switching signal, so as to control the data writing according to the data writing. The write command output by the interface 151 performs a write operation on the single-port random access data memory 110 , that is, writes the data to be stored into the single-port random access data memory 110 . When the data writing interface 151 is connected to the single-port random access data memory 110, the data reading interface 152 and the single-port random access data memory 110 are in a non-conducting state. When the switching signal sent by the switching control circuit is a write-to-write switching signal, a write operation is performed on the single-port random access data memory 110. During this process, the read operation on the single-port random access data memory 110 is prohibited.

In some embodiments, the switching circuit 130 may include a multiplexer, or switches corresponding to the number of interfaces, etc., which are not limited here. For illustration, the switching circuit 130 is a multiplexer as an example. When the switching signal is a read When the switching signal is obtained, the multiplexer connects the data reading interface 152 to the single-port random data memory 110; when the switching signal is a write switching signal, the multiplexer connects the data writing interface 152 to the single-port random data memory 110. .

In some embodiments, the switching control circuit 120 may include a controller, which may include a first output terminal and a second output terminal, and the first output terminal and the second output terminal are respectively connected to the switching circuit 130; wherein, the first output terminal The output terminal is used to output the read switching signal to the switching circuit 130 , and the second output terminal is used to output the writing switching signal to the switching circuit 130 .

It should be understood that the switching control circuit 120 may also include more or less components, which are not specifically limited here.

As an implementation manner, when the switching signal output by the switching control circuit 120 is high level, it can be characterized as a read switching signal; when the switching signal output by the switching control circuit 120 is low level, it can be characterized as a writing switching signal.

As another implementation manner, when the switching signal output by the switching control circuit 120 is low level, it can be characterized as a read switching signal; when the switching signal output by the switching control circuit 120 is high level, it can be characterized as a writing switching signal. .

The embodiment of the present application receives the read switching signal sent by the switching control circuit 120 through the switching circuit 130, and switches the data reading interface 152 to be connected to the single-port random data memory 110 according to the reading switching signal, so as to output according to the data reading interface 152 The read instruction performs a read operation on the single-port random data memory 110; or the switching circuit 130 receives the write switching signal sent by the switching control circuit 120, and switches the data writing interface 151 to the single-port random data memory according to the write switching signal. 110 is connected to perform a write operation on the single-port random access data memory 110 according to the write instruction output by the data write interface 151. The switching control circuit 120 generates a switching signal, and then the switching circuit 130 responds to the switching signal to finally read or write data to the single-port random data memory 110, so that the FIFO storage control circuit 100 achieves asynchronous operation through a single-port random data memory. The effect is to effectively reduce the area of FIFO memory and reduce the cost.

In some embodiments, the FIFO storage control circuit 100 is also used to determine a preset operation according to the received communication instruction, so that the switching control circuit 120 generates a switching signal according to the preset operation.

In this embodiment, prediction can be made through the communication instructions issued when the communication interface performs corresponding operations on the FIFO storage control circuit 100. For example, if the communication interface wants to perform a read operation on the FIFO storage control circuit 100, a read instruction will be issued. , through the read command, it can be predicted that the preset operation is a read operation. If the communication interface wants to perform a write operation on the FIFO storage control circuit 100, a write command will be issued. Through the write command, it can be predicted that the preset operation is writing operation, in this way, after predicting the preset operation, the switching control circuit 120 can determine the switching signal according to the preset operation. If the preset operation is a read operation, the corresponding switching signal is a read switching signal; if the preset operation is a write operation, the corresponding switching signal is a write switching signal.

Among them, the communication interface can be SPI (Serial Peripheral Interface, serial peripheral interface), I2C (Inter-Integrated Circuit, two-wire serial bus), or UART (Universal Asynchronous Receiver/Transmitter, Universal Asynchronous Receiver/Receiver) transmitter), there is no restriction here.

In some embodiments, before the switching circuit 130 transmits the instruction corresponding to the switching signal to the single-port random access data memory 110, the FIFO storage control circuit 100 is also used to synchronize the switching signal to the corresponding clock domain; wherein, the clock domain includes Read operation clock domain or write operation clock domain. In this embodiment, the corresponding clock domain refers to the clock domain opposite to the current switching signal. For example, if the switching signal is a read switching signal, the clock domain opposite to the switching signal is the writing operation clock domain; if the switching signal is a writing switching signal, the clock domain opposite to the switching signal is the reading operation clock domain. After the FIFO storage control circuit 100 predicts the preset operation to be performed, the switching signal corresponding to the preset operation needs to be synchronized to the clock domain opposite to the switching signal, because the current operation of the FIFO storage control circuit 100 is generally the same as the preset operation. Assuming the opposite operation, the clock connected is the clock opposite to the instruction corresponding to the preset operation, and the instruction corresponding to the preset operation is executed. Since the single-port random access data memory 110 has only one set of interfaces, in order to avoid passing through The sudden switching of the instructions transmitted to the single-port random data memory 110 by this set of interfaces will affect data reading or data writing. When changing the instructions transmitted to the single-port random data memory 110, the switching signal can be synchronized to The FIFO stores the clock domain corresponding to the current operation of the control circuit 100, that is, the clock domain opposite to the switching signal, and reserves reaction time for the switching of instructions.

As an implementation manner, the FIFO storage control circuit 100 is used to synchronize the read switching signal to the write operation clock domain. When the switching signal is a read switching signal, the instruction corresponding to the read switching signal is a read instruction, and the preset operation is a read operation, then the current operation of the FIFO storage control circuit 100 is generally a write operation. In order to avoid suddenly To switch the clock, instructions, etc. connected to the FIFO storage control circuit 100, the switching signal can be synchronized to the write operation clock domain first, so that the write operation clock domain stops the write operation. The switching circuit 130 then transmits the read command to the single-port random access data memory 110. This can avoid the impact of sudden switching of instructions on the single-port random access data memory 110 on the reading or writing of data.

As another implementation manner, the FIFO storage control circuit 100 is also used to synchronize the write switching signal to the read operation clock domain. When the switching signal is a write switching signal, the instruction corresponding to the write switching signal is a write instruction, and the preset operation is a write operation, then the current operation of the FIFO storage control circuit 100 is generally a read operation. In order to avoid suddenly To switch the clock, instructions, etc. connected to the FIFO storage control circuit 100, the switching signal can be synchronized to the read operation clock domain first, so that the read operation clock domain stops the read operation, and then the switching circuit 130 transmits the write command to the single-port randomizer. The data memory 110 can avoid the sudden switching of instructions executed on the single-port random access data memory 110, which may affect the reading or writing of data.

In some embodiments, the FIFO storage control circuit 100 also includes a data control circuit 160 and at least one data buffer 140. The data control circuit 160 is connected to the switching control circuit 120 and the data buffer 140 respectively, and is connected to the single-port random data memory 110. , the data control circuit 160 is used to receive a request signal, and when the request signal is inconsistent with the switching signal, perform an operation corresponding to the request signal on the data buffer 140 according to the request signal; wherein the request signal includes a data read request or data Write request. In this embodiment, the data control circuit 160 is also connected to the switching circuit 130, and the data buffer 140 is also connected to the single-port random access data memory 110. During the period of performing the preset operation on the single-port random access data memory 110 according to the instruction corresponding to the switching signal, a request signal inconsistent with the switching signal may be received. However, the preset operation is being performed on the single-port random access data memory 110 at this time, so the The switching signal corresponding to the preset operation is inconsistent with the request signal, so the corresponding operation cannot be performed on the single-port random data memory 110 according to the request signal. To solve this problem, a data control circuit 160 and at least one data cache are set in the FIFO storage control circuit 100 The processor 140 is configured to receive the request signal and perform operations corresponding to the request signal on the data buffer 140 .

As an implementation manner, when the request signal is a data write request and the switching signal is a read switching signal, it means that the request signal and the switching signal are inconsistent, and the data control circuit 160 writes the data to be written according to the data writing request. in the data buffer 140. Since the switching signal is a read switching signal, accordingly, a read operation is performed on the single-port random data memory 110, which is inconsistent with the request signal for a data write request. Therefore, the single-port random data memory 110 cannot execute a data write request. If the corresponding operation is performed, the operation corresponding to the data write request can be performed on the data buffer 140 , that is, the data to be written is first written into the data buffer 140 .

As another implementation manner, when the request signal is a data read request and the switching signal is a write switching signal, it means that the request signal and the switching signal are inconsistent, and the data control circuit 160 reads from the data buffer 140 according to the data read request. Get data. Since the switching signal is a write switching signal, accordingly, the single-port random access data memory 110 performs a write operation, which is inconsistent with the request signal for a data read request, and the single-port random access data memory 110 cannot perform the operation corresponding to the data read request. operation, you can pass the data The buffer 140 is used to perform operations corresponding to the data read request, that is, data is first read from the data buffer 140 .

In this embodiment, the data buffer 140 is equivalent to a register. When performing a read or write operation on the single-port random access data memory 110, another operation will be blocked. This problem can be solved through the data buffer. The data buffer 140 may include a data write buffer 141, may include a data read buffer 142, and may further include a data write buffer 141 and a data read buffer 142.

When the switching circuit 130 performs a read operation on the single-port random access data memory 110 according to the read command output by the data read interface, the data control circuit 160 writes the data to be written into the data write buffer 141 according to the write request. When performing a read operation on the single-port random access data memory 110, since the single-port random access data memory 110 has only one set of interfaces, when there is another write request and the single-port random access data memory 110 is executed, the data write buffer 141 can be used first. The data to be written in the single-port random access data memory 110 is buffered into the data write buffer 141 according to the write request. After the read operation is completed on the single-port random access data memory 110 , the data in the data write buffer 141 is transferred to the single-port random access data memory 110 .

When the switching circuit 130 performs a write operation on the single-port random access data memory 110 according to the write command output by the data write interface, the data control circuit 160 reads data from the data read buffer 142 according to the data read request. When performing a write operation on the single-port random data memory 110, since the single-port random data memory 110 has only one set of interfaces, when there is another read request, the request cannot be executed on the single-port random data memory 110. You can read the data through The fetch buffer 141 will first read data from the data read buffer 141 according to the read request. In order to prevent the data read buffer 141 from being empty, some data can be transferred from the single port random access data memory 110 to the data read buffer 141 before performing a write operation on the single port random access data memory 110 .

In the embodiment of the present application, the data control circuit 160 or the data buffer 140 can be controlled through an enable signal. The enable signal types include read enable and write enable.

As an implementation manner, when the enable information is high level, it can be characterized as read enable, and the data read interface 152 (or an external device connected to the data read interface 152) can read data from the data read buffer 142. Read the stored data; when the enable information is low level, it can be characterized as write enable information, and the data write interface 151 (or an external device connected to the data write interface 151) can write data into the buffer 141 Write the data to be stored.

As another implementation manner, when the enable information is low level, indicating that the enable information is read, the data read interface 152 (or an external device connected to the data read interface 152) can read the data buffer 142 from the data read interface 152. Read the stored data; when the enable information is high level, it is characterized as write enable information, and the data write interface 151 (or an external device connected to the data write interface 151) writes to the data write buffer 141 Enter the data to be stored.

In some embodiments, the data control circuit 160 is also connected to the single-port random access data memory 110 . Among them, the switching circuit 130 executes the single-port random data memory 110 according to the instruction corresponding to the switching signal. After completing the preset operation, the data control circuit 160 is also used to write the data stored in the data buffer 140 into the single-port random data memory 110, or to write the data in the single-port random data memory 110 into the data buffer 140.

As an implementation manner, the default operation is a read operation. After the switching circuit 130 completes the read operation on the single-port random data memory 110, the data control circuit 160 writes the data in the data buffer 140 to the single-port random data memory. 110.

As another implementation manner, the preset operation is a write operation, and the data control circuit 160 controls the data buffer 140 to read the single-port random access data memory 110 after the switching circuit 130 completes the write operation on the single-port random access data memory 110 .

In some embodiments, the switching control circuit is also used to switch the current switching signal after performing the preset operation on the single-port random data memory 110; and to control the single-port random data memory 110 to execute and switch according to the switched signal. The signal corresponds to the preset operation. After performing the preset operation corresponding to the switching signal on the single-port random access data memory 110, as mentioned above, after performing the operation corresponding to the request signal on the data buffer 140 according to the request signal, the actual corresponding object of the request signal is the single-port random access signal. The data memory 110 and the data buffer 140 play a transitional role when the operation corresponding to the request signal cannot be performed on the single-port random data memory 110. Therefore, after performing the preset operation on the single-port random data memory 110, it is necessary to perform the operation according to the request signal. The data buffer performs corresponding processing, so that the switching control signal 120 can switch the current switching signal to be consistent with the request signal, so that the single-port random data memory 110 can execute the switching information according to the switched signal. Corresponding preset operation, the preset operation at this time corresponds to the request signal. For example, if the request signal is a write request, the corresponding preset operation is a write operation; if the request signal is a read request, the corresponding preset operation is a read operation.

As an implementation manner, when the current switching signal is a read switching signal, the switching control circuit 120 switches the reading switching signal to a writing switching signal to perform a writing operation on the single-port random access data memory 110, thereby changing the data buffer The data in 140 is written into the single-port random access data memory 110. In order to perform a write operation corresponding to the write request on the single-port random access data memory 110, after performing a read operation on the single-port random access data memory 110, the read switching signal can be switched to the write switching signal through the switching control circuit 120, And synchronize the write switching signal to the write operation clock domain for subsequent write operations.

For example, please refer to FIG. 3 , the data control circuit 160 includes a first inverter 161 , a second inverter 162 and a first logic gate 163 . The first input end of the first logic gate 163 is connected to the switching control circuit 120 The output terminal and the second input terminal are connected to the output terminal of the first inverter 161, and the output terminal is respectively connected to the input terminal of the second inverter 162 and the input terminal of the data write register 141; the second inverter The output terminal of 162 is connected to the WEN (write enable terminal) of the single-port random access data memory 110 .

After performing the read operation on the single-port random access data memory 110, the switching control circuit 120 switches the original read switching signal to output the write switching signal. At this time, the switching circuit 130 switches the single-port random access data memory 110 according to the write switching signal. The connected interface is switched, the CLK (clock port) is switched from the read clock to the write clock, and the ADR (address port) is switched from the read pointer to the write pointer. Switch CEN (enable port) from read enable to read cache enable.

Taking the write switching signal as a high level as an example, if the data in the data write buffer 141 is not empty at this time, the data can be read from the data write buffer 141, and there is currently no data written into the data. In the write register 141, that is, the write enable is low level, the write enable output is high level after passing through the first inverter 161, and is input to the second input terminal of the first logic gate 163, The write switching information (high level) is input to the first input terminal of the first logic gate 163. After passing through the first logic gate 163, the output is high level, that is, the read cache enable is high level, resulting in a read data cache operation. , read data and write the data cached in the buffer 141, and at the same time, the CEN port of the single-port random data memory 110 is low level, and corresponding operations can be performed on the single-port random data memory 110; the high level output by the first logic gate 163 After passing through the second inverter 162, the output is low level, so that the WEN port that is finally input to the single-port random data memory 110 is low level, and a write operation can be performed on the single-port random data memory 110, and the data will be written into the buffer. The data read in 141 is written into the address of the single-port random data memory 110 pointed to by the pointer of the single-port random data memory 110 through the DIN (data input port). In this way, when a read operation is performed on the single-port random data memory 110, the data cannot be written to the single-port random data memory 110 and the data is cached in the data write buffer 141. After the read operation on the single-port random data memory 110 is completed, Then, it is written to the single-port random access data memory 110.

As another implementation manner, when the current switching signal is a writing switching signal, the switching control circuit 120 switches the writing switching signal to a reading switching signal to perform a reading operation on the single-port random access data memory 110 to control the data cache. The processor 140 reads the data in the single-port random access data memory 110. In order to perform a read operation corresponding to the read request on the single-port random access data memory 110, after performing a write operation on the single-port random access data memory 110, the write switching signal can be switched to the read switching signal through the switching control circuit 120, And synchronize the read switching signal to the read operation clock domain for subsequent read operations.

Exemplarily, referring to FIG. 4 , the data control circuit 160 includes a third inverter 164 , a fourth inverter 165 , a fifth inverter 167 and a second logic gate 166 , a first input of the second logic gate 166 The terminal is connected to the output terminal of the third inverter 164, the second input terminal is connected to the output terminal of the fourth inverter 165, and the output terminal is connected to the input terminal of the data read register 142; The input terminal is connected to the output terminal of the switching control circuit 120 , and the output terminal of the fifth inverter 162 is connected to the WEN (write enable terminal) of the single-port random access data memory 110 .

After performing the write operation on the single-port random access data memory 110, the switching control circuit 120 switches the original write switching signal to output the read switching signal. At this time, the switching circuit 130 switches the single-port random access data memory 110 according to the read switching signal. Switch the connected interface, switch the CLK (clock port) from the write clock to the read clock, switch the ADR (address port) from the write pointer to the read pointer, and switch the CEN (enable port) from the write enable Switch to write cache enable.

Taking the read switching signal as a low level as an example, if the data read buffer 142 is not full, data can still be written to the data read buffer 142, and no data is currently read from the data read buffer 142. Access According to the data, that is, the read enable is low level, the read enable output is high level after passing through the third inverter 164, and is input to the first input terminal of the second logic gate 166 to read the switching information ( low level) after passing through the second inverter 165, the output is high level, and is input to the second input terminal of the second logic gate 166, then the output of the second logic gate 166 is high level, that is, the write cache is enabled. High level, a write data cache operation is generated, and data can be written to the data read buffer 141. At the same time, the CEN port of the single-port random data memory 110 is low level, and the corresponding operation can be performed on the single-port random data memory 110; The WEN port of the five-port inverter 167 input to the single-port random data memory 110 is at a high level, and the read operation can be performed on the single-port random data memory 110. The data is read from the single-port random data memory 110 through DOUT (output data port) and Write to the data read buffer 142. In this way, the data of the single-port random access data memory 110 can be written into the data read buffer 142. When performing a write operation on the single-port random access data memory 110, since the data cannot be read from the single-port random access data memory 110, the data can be read from the cache memory 142. The data is read from the data read buffer 142.

In order to better understand this application, the following takes the communication interface as SPI, the write switching signal as high level, and the read switching signal as low level as an example to respectively conduct the pre-judgment of the read operation and the pre-judgment in this application. The write operation is described below.

For example, please refer to Figure 3. When the SPI performs a read operation on the FIFO storage control circuit 100, it can be predicted through the communication command that a read operation is to be performed, and the switching control circuit 120 selects to read the switching signal ( low level), and synchronizes the read switching signal to the write operation clock domain to prohibit the write operation, and then the switching circuit 130 switches the data reading interface 152 to the single-port random data memory when receiving the read switching signal. 110 connections. The CLK (clock port) of the single-port random data memory 110 is switched to the read clock, the ADR (address port) is switched to the read pointer, and the CEN (enable port) is read enable (high level). A read operation is performed on the single-port random access data memory 110, that is, the data stored in the single-port random access data memory 110 is read. During this process, the write operation on the single-port random access data memory 110 is prohibited. If there is a data write request during this process, the corresponding write enable of the data write buffer 141 is high, and the data to be written in the single-port random access data memory 110 can be cached into the data write buffer 141 .

When the read operation ends, the switching control circuit 120 re-enables the writing operation and synchronizes the writing switching signal to the writing operation clock domain. After receiving the writing switching signal sent by the switching control circuit 120, the switching circuit 130 The CLK (clock port) of the single-port random data memory 110 switches from the read clock to the write clock, the ADR (address port) switches from the read pointer to the write pointer, and the CEN (enable port) switches from the read enable Enable read caching. If the data write buffer 141 is not empty (the data write buffer 141 has data), and there is currently no write data cache operation (the write enable is low level), a read data cache operation is generated, and the data is read. Write the data cached in the buffer 141.

The CEN port of the single-port random data memory 110 is low level, indicating that the single-port random data memory 110 can be read or written. The write switching signal is high level, the write enable is low level, and the data control The circuit 160 is connected to the WEN port of the single-port random access data memory 110, and supplies the WEN port to the WEN port. When the port outputs a low level, the write operation can be performed on the single-port random data memory 110, and the data read from the data write buffer 141 is written to the pointer of the single-port random data memory 110 through the DIN (data input port). The address pointed to by the single-port random access data memory 110.

Similarly, please refer to Figure 4. When the SPI performs a write operation on the FIFO storage control circuit 100, it can be predicted through the communication command that a write operation is to be performed, and the switch control circuit 120 selects the write switch signal (high) according to the write operation. level), and synchronizes the write switching signal to the read operation clock domain to prohibit the read operation, and then the switching circuit 130 switches the data writing interface 152 to the single-port random data memory 110 when receiving the writing switching signal. connect. The CLK (clock port) of the single-port random data memory 110 is switched to the write clock, the ADR (address port) is switched to the write pointer, and the CEN (enable port) is the write enable. A write operation is performed on the single-port random access data memory 110, that is, data is written into the single-port random access data memory 110. During this process, the read operation on the single-port random access data memory 110 is prohibited. If there is a data reading request during this process, the corresponding read and write enable of the data reading buffer 142 is high, and the data can be read from the data reading buffer 142 .

When the write operation ends, the switching control circuit 120 re-enables the read operation and synchronizes the read switching signal to the read operation clock domain. After receiving the read switching signal sent by the switching control circuit 120, the switching circuit 130 The CLK (clock port) of the single-port random data memory 110 switches from the write clock to the read clock, the ADR (address port) switches from the write pointer to the read pointer, and the CEN (enable port) switches from write enable Enable write caching. If the data read buffer 141 is not full and there is currently no data read operation from the data read buffer 142 (the read enable is low level), a write data cache operation occurs, and the data read buffer 142 can be read. Write data in 141.

The CEN port of the single-port random data memory 110 is at a low level, indicating that the single-port random data memory 110 can be read or written. The data control circuit 160 is connected to the WEN port of the single-port random data memory 110 and outputs a high level to the WEN port. level, the single-port random access data memory 110 can perform a read operation, read data from the single-port random access data memory 110 through DOUT (output data port) and write it into the data read buffer 142.

When the read clock stops, it means that the reading operation will not be performed temporarily, and the switching circuit 130 can switch the connection between the data writing interface 151 and the single-port random data memory 110 in advance; when the writing clock stops, it means that the writing operation will not be performed temporarily, and the switching circuit 130 can switch in advance. The circuit 130 can switch the data reading interface 151 to connect to the single-port random data memory 110 in advance; when both the reading and writing clocks are stopped, it means that the reading and writing operations will not be performed temporarily, the data reading interface 152 or the data writing interface 151 can maintain the specified state or restore the initial state.

This designated state means that the data reading interface 152 or the data writing interface 151 remains connected to the single-port random access data memory 110 at the end of the last work.

The above-mentioned application embodiment reads and writes data from time to time to the FIFO storage control circuit 100 through the communication interface, predicts the read operation or write operation, generates a switching signal in the switching control circuit 120, and the switching circuit 130 performs switching control according to the switching control circuit 120. The read switching signal sent by the circuit 120 switches the data read interface 152 to be connected to the single-port random access data memory 110, so as to read according to the read signal output by the data read interface 152. The instruction is to perform a read operation on the single-port random access data memory 110, or the switching circuit 130 switches the data writing interface 151 to be connected to the single-port random access data memory 110 according to the write switching signal sent by the switching control circuit 120, so that the data writing interface 151 The output write command performs a write operation on the single-port random data memory 110, in which the read operation clock and the write operation clock are independent. Only when the switching control circuit 120 outputs a write switching signal can the single-port random data memory 110 be written. A write operation is performed; only when the switching control circuit 120 outputs a read switching signal, the read operation can be performed on the single-port random access data memory 110 . The above-mentioned FIFO storage control circuit 100 uses a single-chip single-port random data memory 110 as the storage unit, which meets the asynchronous requirements of the FIFO storage control device, effectively reduces the area of the FIFO memory, and reduces the cost.

Please refer to FIG. 5 , which is a schematic flowchart of a FIFO storage control method provided by yet another embodiment of the present application. The FIFO storage control method can be applied to the above-mentioned FIFO storage control circuit 100, and the method can include the following steps:

Step S210: Generate a switching signal according to the received communication command. The switching signal includes a read switching signal or a writing switching signal.

Step S220: Transmit the instruction corresponding to the switching signal to the single-port random access data memory 110 according to the switching signal to perform a preset operation on the single-port random access data memory 110, where the instruction includes a read instruction or a write instruction, and the preset operation includes a read operation. or write operation.

For the specific description of the above steps S210-S220, please refer to the specific description of the previous embodiment, and will not be described again in this embodiment.

Please refer to Figure 6. Before step S220, the method also includes:

Step S230: Control the connection status of the data writing interface and the data reading interface to the single-port random access data memory 110 according to the switching signal.

For the detailed description of the above step S230, please refer to the detailed description of the foregoing embodiments, and will not be described again here.

Please refer to Figure 7 in conjunction with this method, which may include the following steps:

Step 210: Generate a switching signal according to the received communication command. The switching signal includes a reading switching signal or a writing switching signal.

Step S240: Connect the data reading interface 152 to the single-port random access data memory 110 according to the read switching signal, so as to perform a read operation on the single-port random access data memory 110 according to the read command output by the data reading interface 152.

For the detailed description of the above step S240, please refer to the detailed description of the foregoing embodiments, and will not be described again here.

Please refer to Figure 8 in conjunction with this method. This method may also include the following steps:

Step S250: Connect the data writing interface 151 to the single-port random data storage according to the writing switching signal. The memory 110 is configured to perform a write operation on the single-port random access data memory 110 according to the write command output by the data write interface 151 .

For the detailed description of the above step S250, please refer to the detailed description of the foregoing embodiments, and will not be described again here.

Please refer to Figure 9 in conjunction. Before step S220, the method also includes:

Step S260: Synchronize the switching signal to the corresponding clock domain; where the clock domain includes a read operation clock domain or a write operation clock domain.

For the detailed description of the above step S260, please refer to the detailed description of the foregoing embodiments, and will not be described again here.

Figure 10 is a schematic structural diagram of a chip provided by this application. As shown in FIG. 10 , the chip 20 includes a FIFO storage control circuit 100 .

Figure 11 is a schematic structural diagram of an electronic device provided by this application. As shown in FIG. 10 , the electronic device 30 includes a FIFO storage control circuit 100 or a chip 20 .

The electronic device 30 may be, but is not limited to, a weight scale, a body fat scale, a nutritional scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a vehicle mounted Chargers, adapters, monitors, USB (Universal Serial Bus, Universal Serial Bus) docking stations, stylus pens, true wireless headphones, car central control units, cars, smart wearable devices, mobile terminals, smart home devices. Smart wearable devices include but are not limited to smart watches, smart bracelets, and cervical massagers. Mobile terminals include but are not limited to smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include but are not limited to smart sockets, smart rice cookers, smart sweepers, and smart lights.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present application, but not to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will understand that: it can still Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent substitutions are made to some of the technical features; however, these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions in the embodiments of the present application.

Claims

A FIFO storage control circuit, which is characterized by including:

Single port random access data memory;

A switching control circuit for generating a switching signal, the switching signal including a read switching signal or a writing switching signal;

A switching circuit configured to transmit an instruction corresponding to the switching signal to the single-port random access data memory according to the switching signal to perform a preset operation on the single-port random access data memory, wherein the instruction includes a read instruction or Write instructions, the preset operations include read operations or write operations.
The FIFO storage control circuit according to claim 1, characterized in that the FIFO storage control circuit further includes a data writing interface and a data reading interface;

The switching circuit is respectively connected to the data writing interface and the data reading interface, and is used to control the connection between the data writing interface, the data reading interface and the single-port random data memory according to the switching signal. Connection Status.
The FIFO storage control circuit according to claim 2, wherein the switching circuit is used to connect the data reading interface to the single-port random data memory according to the reading switching signal, so as to The read command output by the read interface performs a read operation on the single-port random access data memory.
The FIFO storage control circuit according to claim 2, wherein the switching circuit is used to connect the data writing interface to the single-port random data memory according to the writing switching signal, so as to The write instruction output by the write interface performs a write operation on the single-port random data memory.
The FIFO storage control circuit according to claim 2, characterized in that, before the switching circuit transmits the instruction corresponding to the switching signal to the single-port random data memory, the FIFO storage control circuit is also used to The switching signal is synchronized to a corresponding clock domain; wherein the clock domain includes a read operation clock domain or a write operation clock domain.
The FIFO storage control circuit according to claim 5, wherein the switching signal is a read switching signal, and the FIFO storage control circuit is used to synchronize the read switching signal to the write operation clock domain. .
The FIFO storage control circuit according to claim 5, wherein the switching signal is a write switching signal, and the FIFO storage control circuit is used to synchronize the write switching signal to the read operation clock domain. .
The FIFO storage control circuit according to claim 5, characterized in that the FIFO storage control circuit further includes a data control circuit and at least one data buffer;

The data control circuit is respectively connected to the switching control circuit and the data buffer;

The data control circuit is used to receive a request signal, and when the request signal and the switching signal do not When consistent, perform an operation corresponding to the request signal on the data buffer according to the request signal; wherein the request signal includes a data read request or a data write request.
The FIFO storage control circuit according to claim 8, wherein the request signal is a data write request, and when the switching signal is a read switching signal, the data control circuit changes the data according to the data writing request. The data to be written is written into the data buffer.
The FIFO storage control circuit according to claim 9, wherein the data buffer includes a data write buffer;

When the switching circuit performs a read operation on the single-port random access data memory according to the read instruction output by the data read interface, the data control circuit writes the data to be written into the data memory according to the write request. The above data is written into the buffer.
The FIFO storage control circuit according to claim 8, wherein the request signal is a data read request, and when the switching signal is a write switching signal, the data control circuit switches from Read data from the data buffer.
The FIFO storage control circuit according to claim 9, wherein the data buffer includes a data read buffer;

When the switching circuit performs a write operation on the single-port random data memory according to the write instruction output by the data write interface, the data control circuit reads data from the data read buffer according to the data read request. Read data.
The FIFO storage control circuit according to claim 8, characterized in that the data control circuit is also connected to the single-port random data memory;

After the switching circuit performs the preset operation on the single-port random data memory, the data control circuit is also used to write the data stored in the data buffer to the single-port random data memory, or , writing the data in the single-port random access data memory to the data buffer.
The FIFO storage control circuit according to claim 13, wherein the preset operation is a read operation;

The data control circuit is also configured to write the data in the data buffer to the single-port random data memory after the switching circuit completes the read operation on the single-port random data memory.
The FIFO storage control circuit according to claim 13, wherein the preset operation is a write operation;

The data control circuit is also used to control the data buffer to read the data in the single-port random data memory after the switching circuit completes the write operation on the single-port random data memory.
The FIFO storage control circuit according to any one of claims 1-15, characterized in that the switching control circuit is also used for:

After performing the preset operation on the single-port random data memory, the current switching signal is row switching; and

The single-port random access data memory is controlled according to the switched signal to perform the preset operation corresponding to the switched signal.
The FIFO storage control circuit according to any one of claims 1 to 15, characterized in that the FIFO storage control circuit is also used to determine the preset operation according to the received communication instruction, so that the switching control circuit is based on The preset operation generates the switching signal.
A FIFO storage control method, characterized in that it is applied to the FIFO storage control circuit according to any one of claims 1-17, and the method includes:

Generate a switching signal according to the received communication command; the switching signal includes a read switching signal or a writing switching signal;

According to the switching signal, instructions corresponding to the switching signal are transmitted to the single-port random access data memory to perform preset operations on the single-port random access data memory, wherein the instructions include read instructions or write instructions, and the Preset operations include read operations or write operations.
The method according to claim 18, characterized in that the connection status of the data writing interface and the data reading interface and the single-port random access data memory is controlled according to the switching signal.
The method according to claim 19, characterized in that a data reading interface is connected to the single-port random data memory according to the read switching signal, so that the single-port random data memory is read according to a read instruction output by the data reading interface. Random data memory performs read operations.
The method according to claim 19, characterized in that a data writing interface is connected to the single-port random data memory according to the writing switching signal, so that the single-port random data memory is configured according to a write instruction output by the data writing interface. The random access data memory performs write operations.
The method according to claim 18, characterized in that, before the switching circuit transmits the instruction corresponding to the switching signal to the single-port random data memory, the switching signal is synchronized to the corresponding clock domain; wherein , the clock domain includes a read operation clock domain or a write operation clock domain.
A chip, characterized in that the chip includes at least the FIFO storage control circuit as described in any one of the above claims 1-17.
An electronic device, characterized in that the electronic device includes a device body and a chip according to claim 23 or a FIFO storage control circuit according to any one of claims 1 to 17 provided in the device body. .