JP2734141B2 - Packet switch - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet switch, and more particularly, to a structure of a packet switch capable of outputting one packet to a plurality of output lines.

[Conventional technology]

Conventionally, when a packet input from a plurality of incoming lines is switched and output to a plurality of outgoing lines, a method of configuring a packet switch using a time division multiplexing / demultiplexing circuit and a memory circuit for temporarily storing packets has been adopted. I was

FIG. 3 is a block diagram for explaining an operation of an example of a conventional packet switch. Referring to FIG. 3, this conventional packet switch is provided with a time division multiplexer 201.
, A memory circuit 202, and a separating circuit 203 for sorting and outputting packets to target outgoing lines. A plurality of packets input to the packet switch from the plurality of input lines 204 and 205 are time-division multiplexed by the time-division multiplexer 201 and output to the internal bus 206. After temporarily storing the time-division multiplexed packets in the memory circuit 202, the separation circuit 203
Reads the packets temporarily stored in the memory circuit 202 through the internal bus 207 in an appropriate order according to a certain algorithm, and outputs the packets to predetermined output lines 208 and 209. This allows
A packet switch that outputs packets from arbitrary incoming lines 204 and 205 to arbitrary outgoing lines 208 and 209 is realized.

[Problems to be solved by the invention]

In this conventional packet switch, it is necessary to read out the packets temporarily stored in the memory circuit 202 by a certain algorithm, and in particular, a broadcast function of outputting one packet to a plurality of output lines at the same time inside the switch is required. However, there is a problem that an algorithm satisfying this requirement is complicated.

[Means for solving the problem]

According to the present invention, a time-division multiplexer for time-division multiplexing packet signals from a plurality of input lines, and an address filter for determining an output line to output a packet based on address information of the time-division multiplexed packet are provided. A memory circuit for temporarily storing the packets, and a separating circuit for distributing the packets temporarily stored and read out by the memory circuit for each target output line. The memory circuit is segmented for each switch output line. After temporarily storing the packets in the segment on the memory circuit corresponding to the outgoing line to be output determined by the address filter, reading the packets one by one from each of the segments and distributing the packets by the separation circuit. A packet switch for outputting to each outgoing line, wherein the memory circuit reads each segment. An address decoder and a write control circuit for simultaneously writing only data to an arbitrary address position of an arbitrary number of segments, and writing the time-division multiplexed input packet to a plurality of segments of the memory circuit at the same time. Thus, a packet switch characterized by the following is obtained.

〔Example〕

Next, the present invention will be described with reference to FIGS.

FIG. 1A is an overall configuration diagram showing one embodiment of the packet switch of the present invention. Referring to FIG. 1 (a),
The packet switch of the present embodiment includes a time division multiplexer 101,
Address filter 10 for determining which output line the time-division multiplexed packet is to be output based on the address information.
2, a memory circuit 103 for temporarily storing packets, and a separating circuit 104 for distributing the packets to target outgoing lines and outputting the outgoing lines. Reference numerals 105,..., 106 indicate segments obtained by dividing the memory circuit 103 for each output line.
, 108 indicate a plurality of incoming lines to which the packet is input, reference numerals 109, 110, 111 indicate internal buses of the switch, and reference numerals 112,..., 113 indicate a plurality of outgoing lines from which the packet is output.

FIG. 1 (b) is a diagram for explaining the operation of the time division multiplexer in FIG. 1 (a). Referring to FIG. 1 (b), input packets 114 from a plurality of incoming lines 107,.
, 115 are time-division multiplexed by the time-division multiplexer 101 and output to the internal bus 109 (time-division multiplexed packet 11
8,…, 119). Here, address information 116, 117 indicating a target outgoing line is added to each of the input packets 114, 115, respectively. Input packets 114 and 115 are input to the switch one packet at a time from each input line during a packet input cycle. On the internal bus 109, this packet input cycle is divided into the same number of unit times (hereinafter referred to as time slots) as the plurality of incoming lines 107,..., 108, and packets 118,. Assign 119.

FIG. 1 (c) is a diagram for explaining the operation of the address filter in FIG. 1 (a). Referring to FIG. 1 (c), the packet 11 multiplexed on the internal bus 109 is time-division multiplexed.
, 119 are input to the address filter 102, the address filter 102 determines an output line to be output based on the address information 116,..., 117 (shown in FIG. 1B).
At this time, the same judgment is made for packets to be output to a plurality of outgoing lines. Thereafter, the address filter 102 is connected to the internal bus 110.
, 121 are transmitted.

FIG. 1 (d) is a diagram for explaining the write operation to the memory circuit in FIG. 1 (a). Referring to FIG. 1D, the memory circuit 103 is segmented for each output line of the switch. Each segment 105, ..., 106 is the first
The packets to be output to the outgoing lines 112,..., 113 shown in FIG. The packets allocated to the time slots 120,..., 121 on the internal bus 110 are temporarily stored in the segment corresponding to the output line to be output. At this time,
If a packet is output to a plurality of outgoing lines, the same packet is written to a corresponding plurality of segments. here,
The memory circuit 103 can write data simultaneously to an arbitrary address position independently in a plurality of segments.

FIG. 1 (e) is a diagram for explaining a read operation from the memory circuit in FIG. 1 (a). Referring to FIG. 1 (e), each segment 105,.
The packets stored in 6 are output to the internal bus 111 one by one from each segment. Packet from segment 105
Packets 122 from 122 and segment 106 are sent to internal bus 1
The signals are sequentially output to 11 and input to the separation circuit 104. Each packet is time-division multiplexed on the internal bus 111. The order of the time slots defined on the internal bus 111 corresponds to the outgoing line, and packets are read one by one from each segment of the memory circuit 103 in order. The separating circuit 104 outputs the packets 122,..., 123 input in each time slot to the outgoing lines 112,. The output packet 124 and the like are obtained by extracting the packet 122 and the like multiplexed on the internal bus 111 by the separation circuit 104.

FIG. 2 is a circuit block diagram showing an example of the memory circuit shown in FIG. 1 (a). In FIG. 2, only a circuit for writing is shown, and a circuit for reading is not shown. The conventional memory circuit 202 shown in FIG.
The same circuit as above may be used. In FIG. 2, reference numerals 301, 30
, 303 indicate address decoders and write control circuits, reference numerals 304, 305,..., 306 indicate memory cell areas for storing actual data, and reference numerals 307, 308,. , 306 indicate word lines for selecting any of a plurality of addresses, and reference numerals 310 and 311 denote write data of the memory circuit as bit lines 312.
Shows the driver to be driven. Also, reference numerals 313, 31
5 and 317 are address signals for specifying one of the word lines 307, 308 and 309, respectively,
316 and 318 are memory cell areas 304, 305 and 3 respectively
This is a write control signal for designating whether or not to write data in 06, and reference numerals 319 and 320 are write data of the memory circuit. Address decoder and write control circuit 301
, Memory cell region 304 and word line 307 constitute one segment, and address decoder and write control circuit 30
2, the memory cell region 305, and the word line 308 constitute one segment, and similarly, the address decoder / write control circuit 303, the memory cell region 306, and the word line 309 constitute one segment. Here, each memory cell area 30
The segments 4,305 and 306 will be referred to as segment 1, segment 2 and segment N, respectively.

On the other hand, the drivers 310 and 311 and the bit line 312 are shared by all the segments 1, 2,..., N. The write data 319 and 320 are driven to the respective bit lines 312 by the drivers 319 and 320. For example, if it is necessary to write data to segment 1, if writing to segment 1 and designation of an address position to write data are performed from outside the memory circuit by a write control signal 314 and an address signal 313, an address decoder and a write control circuit 301 is the address signal 313
Is decoded, and one of the word lines 307 is activated. By this activation, the data on the bit line 312 is transferred to the memory cell area 304 connected to the activated word line.
Is written to the memory cells in the cell. At the same time, the writing control signal
By specifying writing and an address position where data is to be written by using the address signals 316 and 318 and the address signals 315 and 317, the same data can be arbitrarily written to an arbitrary address position.

As described above, in the present embodiment, it is possible to write data to an arbitrary address position of an arbitrary number of segments at the same time if necessary. Therefore, the input packet is written to a plurality of address positions of the memory circuit at the same time (the packet is duplicated on the memory circuit), and the broadcast of the packet is easily performed.

〔The invention's effect〕

As described above, the present invention divides a memory circuit for temporarily storing an input packet into segments and stores packets to be output to each output line in a segment corresponding to the output line, so that the same packet is stored in all segments. Since writing can be performed at the same time, there is an effect that a packet can be broadcast in the switch by read control using a simple algorithm.

[Brief description of the drawings]

FIG. 1 (a) is an overall configuration diagram showing an embodiment of a packet switch of the present invention, and FIGS. 1 (b) and 1 (c) show operations of a time division multiplexer and an address filter in FIG. 1 (a), respectively. FIGS. 1 (d) and 1 (e) are diagrams for explaining a write operation to a memory circuit and a read operation from a memory circuit in FIG. 1 (a), respectively, and FIG. FIG. 1A is a circuit block diagram showing an example of a memory circuit, and FIG. 3 is a block diagram for explaining the operation of an example of a conventional packet switch. 101, 102: time-division multiplexer, 102: address filter, 103, 202: memory circuit, 104, 203: separating circuit, 10
5,106 …… Segment, 107,108,204,205 …… Incoming line, 109,
110,111 …… Internal bus, 112,113,208,209 …… Outbound, 114,
115 …… Input packet, 116,117 …… Address information, 118,
119,120,121,122,123 …… Time-division multiplexed packet, 1
24, 125 ... output packets, 301, 302, 303 ... address decoders and write control circuits, 304, 305, 306 ... memory cell areas, 307, 308, 309 ... word lines, 310, 311 ... data drivers.

Claims (1)

(57) [Claims] 1. A time division multiplexer for time division multiplexing packet signals from a plurality of input lines, an address filter for judging an output line to output a packet based on address information of the time division multiplexed packet, A memory circuit for temporarily storing the packets, and a separating circuit for sorting the packets temporarily stored and read out by the memory circuit for each target output line, and segmenting the memory circuit for each switch output line. After temporarily storing the packets in the segment on the memory circuit corresponding to the outgoing line to be output determined by the address filter, reading the packets one by one from each segment and distributing the packets by the separation circuit. A packet switch for outputting to each output line, wherein the memory circuit writes each of the segments. An address decoder and a write control circuit for simultaneously writing data at an arbitrary address position of an arbitrary number of segments are provided, and the time-division multiplexed input packet is written to a plurality of segments of the memory circuit at the same time. Characterized packet switch.