JPH0520011B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an intermediate relay device of a PCM communication system that uses a PCM multiplexed signal generated by synchronously multiplexing a plurality of low-level PCM signals as a transmission path signal.

[Conventional technology]

Conventionally, as an example of a PCM intermediate relay device that has the function of separating and inserting this type of overhead bit data, Fig. 2 shows a PCM multiplexed signal in which two low-level PCM signals having a frame structure are synchronously multiplexed as a transmission line signal. A functional block diagram of an intermediate relay device in the case of the following is shown.

In FIG. 2, a PCM multiplex signal a that has undergone attenuation waveform distortion due to propagation through a transmission path is input to an input terminal 201, and a PCM multiplex signal a that has been identified and reproduced by self-synchronization is obtained in a receiving circuit 202. This output is sent to the separation circuit 203 as a low-order PCM signal 2 which is 1/2 the speed of the input PCM multiplex signal.
In the selection circuit 204, one becomes the direct input signal p to the multiplex circuit 205, and the other becomes the input q to the synchronization circuit 206. From the synchronization circuit 206 to the selection circuit 20 so that the signal p and the signal q are always low-level PCM signals of different systems.
A control signal h is given to 4.

The synchronization circuit 206 performs frame synchronization on the low-order PCM input signal q by detecting a predetermined pattern of frame bits, takes out a specific bit string in the overhead bits as separated data c, and inserts it. An operation is performed in which data d is inserted into the overhead bit and a new low-order PCM signal n is output. Furthermore, the synchronization circuit 206 determines whether the input signal q is a low-order PCM signal of a system in which overhead bit data should be separated and inserted, based on the content of a specific system confirmation bit in the overhead bits, and outputs the control signal. It also has a function to output h.

Next, in the multiplex circuit 205, the low-level PCM signal n into which the contents of the overhead bit data have been separated and inserted, and the low-level PCM signal n which is not subjected to any data processing.
The PCM signal p is parallel-serial converted to generate a PCM multiplex signal i having a speed twice as high as the lower PCM signal speed. The transmitting circuit 207 converts this PCM multiplexed signal i into a form that matches the transmission path and sends it out from the output terminal 208.

The above is a conventional example in which a signal obtained by synchronously multiplexing two low-level PCM signals having a frame structure as a transmission signal is used as a transmission line signal. FIG. 3 shows a conventional example in which the intermediate relay device includes a frame generation circuit and an oscillator that operates when the received signal is abnormal.

In Fig. 3, from the transmission line to the input end 301
In the receiving circuit 302 where the PCM signal a is input,
An identified and reproduced PCM signal is obtained. Since this output is a PCM signal that already has a frame structure, it is directly input to the synchronization circuit 303, where frame synchronization is achieved, and part of the overhead bit data is separated to the outside as separated data c.

In the frame generation circuit 304, the output data l from the synchronization circuit 303 and the inserted data d from the outside, other than the separated data c, are incorporated into a newly generated frame structure and output via the transmission circuit 305. The signal is sent out from the end 306 to the transmission path. As the basic timing of the frame generation circuit 304, the clock signal e extracted from the received signal in the receiving circuit 302 is normally used via the selection circuit 307, but the received signal disconnection information f detected in the receiving circuit 302 or the synchronization circuit The output h of the control circuit 308 is inverted by the out-of-synchronization information r detected in the oscillator 303, and the selection circuit 307
Select the output j of .

That is, in the intermediate relay device of this conventional example, even when the reception signal is cut off or synchronization is lost due to an abnormality in the content of the reproduction output of the reception circuit, the built-in oscillator 309
operates, the frame generation circuit 304 operates normally, and the sending of the insertion data d is ensured. As a specific application example of this conventional technology,
"Development of 140Mb/s (5B6B) optical communication equipment"
(IEICE CS85-9, Hitoshi Sato et al.).

[Problem that the invention seeks to solve]

The first conventional intermediate relay device shown in FIG.
This has the disadvantage that the sending of the insertion data d also stops.

Furthermore, when the second conventional intermediate relay device shown in FIG. It obviously doesn't work because there is no separation circuit to break it down into PCM signals.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned two drawbacks of the prior art, to ensure the overhead bit data insertion operation even when a synchronously multiplexed PCM multiplex signal is used as a transmission line signal, and to An object of the present invention is to provide an extremely high-quality intermediate relay device that does not adversely affect the relay transmission of low-level PCM signals that do not undergo any processing.

[Means for solving problems]

The PCM intermediate relay device according to the present invention is generated by synchronously multiplexing a plurality of low-level PCM signals each consisting of one system of PCM pulse trains that constitute a frame.
In intermediate relay equipment for PCM communication systems that use PCM multiplexed signals as transmission path signals, the received and regenerated PCM multiplexed signals are serial-parallel converted to the original multiple lower order signals.
A separation circuit that separates the signals into PCM signals, multiple synchronization circuits that synchronize frames by inputting each separated low-order PCM signal and take out part of the data in the overhead bits incorporated in the frame, and a frame generation circuit that generates a frame signal having the same structure as a PCM signal frame;
an oscillator for providing basic timing for the frame generation circuit; a first selection circuit for selecting a timing signal extracted from a received signal and an output from the oscillator and providing it to the frame generation circuit; a plurality of second selection circuit groups for selecting low-order PCM signals from the circuits and output data signals from each synchronous circuit; and at least one low-order selection circuit group selected by the second selection circuit groups.
at least one insertion circuit for inserting low-speed data from the outside as part of the overhead bits of a frame of a PCM signal;
a multiplex circuit for parallel-to-serial converting the signal and a directly output low-order PCM signal with no external data inserted among the outputs of the second selection circuit group; and a control circuit that controls the first selection circuit and the second selection circuit group based on the signal shown.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a PCM intermediate relay device according to the present invention. In this example, like the conventional example shown in Fig. 2, two systems of low-order PCM signals having a frame structure are synchronously multiplexed.
Let us consider the case where a PCM multiplex signal is used as a transmission line signal.

A PCM multiplex signal a, which has undergone attenuation and waveform distortion while propagating through the transmission path, is input to the input end 101.
It is identified and reproduced in the receiving circuit 102. This output is serial-parallel converted in a separation circuit 103 and separated into two low-order PCM signal systems having a frame structure, and then input to a synchronization circuit 104 and a synchronization circuit 105. At the same time that frame synchronization is established, part of the overhead bit data is taken out as separate data C, C'. Further, the frame generation circuit 106 generates a new frame structure in accordance with the timing determined by the timing signal k, and sends it out in place of the out-of-synchronization low-level PCM signal.

In normal times, that is, when both low-level PCM signals are synchronized in the synchronization circuits 104 and 105, the selection circuits 107 and 108 are connected to the synchronization circuits 104 and 105, respectively.
Select output data l, m from 4,105,
Input to insertion circuits 109 and 110. Here, the externally inserted data d and d' are taken into the overhead bits of the low-order PCM signal frame of each system, and their outputs n and p are parallel-serial converted in the multiplex circuit 111 to double the information rate. The signal is then sent from the transmitting circuit 112 to the transmission path via the output terminal 113.

Next, the operation when the received signal is abnormal will be explained. The contents of the received signal abnormality are: firstly, the received signal is interrupted, secondly, there is a received signal but there is no normal frame pattern in the low-level PCM signals of both two systems, and thirdly, there is a low-level PCM signal of only one system. It is classified if there is no normal frame pattern.

First of all, when the received signal is cut off, the receiving circuit 102
The timing signal e outputted from the circuit is also cut off.

At this time, the reception circuit 102 receives reception signal disconnection information f.
is sent to the control circuit 114. Control circuit 114
receives the received signal interruption information f, and inverts the control signals g, h, and h'. As a result, the selection circuit 115 selects the output j of the oscillator 116, and the frame generation circuit 106 operates at this timing. On the other hand, the selection circuits 107 and 108 also select the output of the frame generation circuit 106, which becomes the frame of each low-order PCM signal to be sent out, and the insertion circuits 109 and
Insertion of external insertion data d, d' at 110 is ensured. Therefore, the normal signal b sent out from the sending end 113 is also reproduced.

In the second abnormal state, that is, when there is no normal frame pattern in the lower PCM signals of both systems,
Frame synchronization is not established in both synchronization circuits 104 and 105. Therefore, the synchronous circuit 10
4 and 105 send out-of-synchronization information r and r' to the control circuit 114, respectively. The control circuit 114 is
Upon receiving both out-of-synchronization information r and r', the control signals g, h and h' are inverted. Therefore, in exactly the same way as when the first received signal is cut off, each selection circuit is controlled, and the output of the frame generation circuit 106 operated by the timing output of the oscillator 116 becomes the sending signal, and the insertion data d and d' are Delivery is ensured.

Third abnormal condition, low level PCM of only one system
If the signal does not have a normal frame pattern, for example, the frame pattern of the low-order PCM signal on the synchronization circuit 104 side is normal, but the low-order PCM signal on the synchronization circuit 105 side does not have a normal frame pattern. Although frame synchronization is established in circuit 104, frame synchronization is not established in synchronization circuit 105.

Therefore, the synchronization circuit 104 does not send out the out-of-synchronization information r, but the synchronization circuit 105 does not send out out-of-synchronization information r.
Send r′. At this time, since the control circuit 114 can determine that the timing output signal e of the receiving circuit 102 is normal, it does not invert the control signal g. Therefore, the selection circuit 115 selects the timing signal e, thereby causing the frame generation circuit 106 to operate. On the other hand, the control circuit 114
Since the output data l can be determined to be normal, the control signal h is not inverted. Therefore, the selection circuit 107
Choose a side. On the other hand, since the control circuit 114 can determine that the output data m of the synchronization circuit 105 is abnormal, it inverts the control signal h'. Therefore, selection circuit 1
08 selects the output of the frame generation circuit 106. Therefore, the frames of the low-order PCM signals input to the insertion circuits 109 and 110 are both normal, and as in other abnormal states, the insertion data d,
The transmission of d′ is ensured.

Note that the synchronization circuits 104 and 105 output control signals s and s' for interchanging the output data q and q' of the separation circuit 103 based on the information of the system instruction bit in the overhead bit.
Furthermore, even if synchronization is lost due to a failure in the synchronization circuits 104, 105, the same treatment as in the case of an abnormality in the received signal is taken, and the transmission of inserted data is ensured.

Further, in the above embodiment, the selection circuits 107 and 108
The outputs of are input to the insertion circuits 109 and 110, respectively, but it is also possible to input only the output of the selection circuit 107 to the insertion circuit 109 and input the output of the selection circuit 108 directly to the multiplexing circuit 111.

〔Effect of the invention〕

As explained above, the present invention provides low-level
PCM received and regenerated in an intermediate repeater of the PCM communication system, which uses a high-level PCM multiplexed signal generated by synchronously multiplexing multiple PCM signals as a transmission path signal.
Convert multiplexed signals to serial/parallel to convert multiple original low-order signals
A separation circuit that separates into PCM signals, a frame synchronization circuit that receives each separated low-order PCM signal as input, and a frame generation circuit that generates a frame signal having the same structure as the frame of the low-order PCM signal are provided. an oscillator for providing basic timing of the frame generation circuit, and a first oscillator for selecting a timing signal extracted from a received signal and an output from the oscillator and providing it to the frame generation circuit.
a plurality of second selection circuits for selecting the frame generation circuit output and the output data signal from each synchronization circuit; and a frame overhead of the at least one low-order PCM signal selected here. Single or multiple insertion circuits that insert low-speed data from multiple parts as part of a bit, and a low-level PCM signal of the output of these insertion circuits, or a low-level PCM signal of the output of the insertion circuit and the output of the second selection circuit group. All selection circuits are controlled from a multiplex circuit that converts directly output low-level PCM signals into parallel series without inserting external low-speed data, a signal indicating reception input disconnection, and a signal indicating loss of synchronization in the plurality of synchronization circuits. By providing a control circuit, it is possible to ensure the transmission of data inserted into external overhead bits even in the case of any kind of received signal abnormality, and the synchronization state of all low-level PCM signals can be maintained. Since it is constantly monitored, it has the effect of ensuring extremely stable timing signal selection and bit synchronization when transmitting multiple low-level PCM signals.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of a PCM intermediate relay device according to the present invention, and FIGS.
The figures are block diagrams showing the configurations of a first conventional example and a second conventional example of a conventional PCM intermediate relay device, respectively. 101...Reception signal input terminal, 102...Reception circuit, 103...Separation circuit, 104, 105...Synchronization circuit, 106...Frame generation circuit, 107,
108... Selection circuit, 109, 110... Insertion circuit, 111... Multiplex circuit, 112... Transmission circuit,
113... Transmission signal output terminal, 114... Control circuit, 115... Selection circuit, 116... Oscillator.

Claims (1)

[Claims] 1 A PCM multiplexed signal generated by synchronously multiplexing multiple low-order PCM signals each consisting of one system of PCM pulse trains constituting one frame is used as a transmission line signal.
In an intermediate relay device of a PCM communication system, a separation circuit converts the received and regenerated PCM multiplexed signal into serial-parallel and separates it into a plurality of original low-order PCM signals;
There are multiple synchronization circuits that input each separated low-order PCM signal to perform frame synchronization and take out part of the data in the overhead bits incorporated in the frame to the outside, and a synchronization circuit that has the same structure as the frame of the low-order PCM signal. a frame generation circuit for generating a frame signal; an oscillator for providing basic timing for the frame generation circuit; and a frame generation circuit for selecting a timing signal extracted from a received signal and an output from the oscillator and providing it to the frame generation circuit. a first selection circuit and a lower level from the frame generation circuit;
a plurality of second selection circuit groups for selecting a PCM signal and an output data signal from each synchronous circuit; and at least one lower PCM signal frame overhead bit selected by the second selection circuit groups. at least one insertion circuit that inserts low-speed data from the outside as part of the insertion circuit, and inserts external data among the low-level PCM signals of the outputs of these insertion circuits or the low-level PCM signals of the output of the insertion circuit and the output of the second selection circuit group. Direct output low PCM
a control circuit that controls the first selection circuit and the second selection circuit group based on a signal indicating disconnection of reception input and a signal indicating out-of-synchronization in the plurality of synchronization circuits; and when the control circuit receives a signal indicating that the reception input is disconnected, the first selection circuit selects the output from the oscillator, and the second selection circuit group selects the output from the frame generation. controlling the circuit to select a low-level PCM signal from the circuit, and controlling the first selection circuit to select a timing signal extracted from the received signal when the signal indicating the receiving input disconnection is not received; When each of the second selection circuits receives a signal indicating the out-of-synchronization from the corresponding synchronization circuit, it selects the low-order PCM signal from the frame generation circuit, and selects the low-order PCM signal from the corresponding synchronization circuit. A PCM intermediate relay device, characterized in that when a signal indicating a deviation is not received, control is performed to select the output data signal from the corresponding synchronization circuit.