JPS6116641A - Automatic multiplex delay system - Google Patents

Automatic multiplex delay system

Info

Publication number
JPS6116641A
JPS6116641A JP13645184A JP13645184A JPS6116641A JP S6116641 A JPS6116641 A JP S6116641A JP 13645184 A JP13645184 A JP 13645184A JP 13645184 A JP13645184 A JP 13645184A JP S6116641 A JPS6116641 A JP S6116641A
Authority
JP
Japan
Prior art keywords
delay
highways
correcting circuit
105b
108b
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13645184A
Inventor
Hiroshi Inomata
Shohei Sato
Original Assignee
Nec Corp
Nec Eng Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp, Nec Eng Ltd filed Critical Nec Corp
Priority to JP13645184A priority Critical patent/JPS6116641A/en
Publication of JPS6116641A publication Critical patent/JPS6116641A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/062Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
    • H04J3/0629Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators in a network, e.g. in combination with switching or multiplexing, slip buffers

Abstract

PURPOSE:To set automatically the delay of a transmission line by correcting the delay time of the transmission line of multiple constitution through firmware during initialization, and holding data on it. CONSTITUTION:A delay correcting circuit 103 receives input signals from highways 105a-108a and judges how long the highway input signals need to be delayed on the basis of memory data, thereby outputting highway output signals to highways 105b-108b. When initializing operation (POW ON RESET) is performed, a pilot pattern signal outputted from the delay correcting circuit 103 is monitored by a microprocessor 102 and memory contents are updated until a pilot pattern is outputted to the highways 105b-108b at the same time. The delay correcting circuit 103 varies the delay time successively when the memory contents are altered.
JP13645184A 1984-07-03 1984-07-03 Automatic multiplex delay system Pending JPS6116641A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13645184A JPS6116641A (en) 1984-07-03 1984-07-03 Automatic multiplex delay system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13645184A JPS6116641A (en) 1984-07-03 1984-07-03 Automatic multiplex delay system

Publications (1)

Publication Number Publication Date
JPS6116641A true JPS6116641A (en) 1986-01-24

Family

ID=15175414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13645184A Pending JPS6116641A (en) 1984-07-03 1984-07-03 Automatic multiplex delay system

Country Status (1)

Country Link
JP (1) JPS6116641A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5903257A (en) * 1995-10-09 1999-05-11 Nintendo Co., Ltd. Operating device and image processing system using same
US5919092A (en) * 1994-08-02 1999-07-06 Nintendo Co., Ltd. Manipulator for game machine
US5963196A (en) * 1995-05-10 1999-10-05 Nintendo Co., Ltd. Image processing system utilizing analog joystick
US5973704A (en) * 1995-10-09 1999-10-26 Nintendo Co., Ltd. Three-dimensional image processing apparatus
US5984785A (en) * 1995-05-10 1999-11-16 Nintendo Co., Ltd. Operating device with analog joystick
US6002351A (en) * 1995-11-10 1999-12-14 Nintendo Co., Ltd. Joystick device
US6239806B1 (en) 1995-10-09 2001-05-29 Nintendo Co., Ltd. User controlled graphics object movement based on amount of joystick angular rotation and point of view angle
US6241610B1 (en) 1996-09-20 2001-06-05 Nintendo Co., Ltd. Three-dimensional image processing system having dynamically changing character polygon number
US6283857B1 (en) 1996-09-24 2001-09-04 Nintendo Co., Ltd. Three-dimensional image processing apparatus with enhanced automatic and user point of view control

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5919092A (en) * 1994-08-02 1999-07-06 Nintendo Co., Ltd. Manipulator for game machine
US5963196A (en) * 1995-05-10 1999-10-05 Nintendo Co., Ltd. Image processing system utilizing analog joystick
US5984785A (en) * 1995-05-10 1999-11-16 Nintendo Co., Ltd. Operating device with analog joystick
US5903257A (en) * 1995-10-09 1999-05-11 Nintendo Co., Ltd. Operating device and image processing system using same
US5973704A (en) * 1995-10-09 1999-10-26 Nintendo Co., Ltd. Three-dimensional image processing apparatus
US6239806B1 (en) 1995-10-09 2001-05-29 Nintendo Co., Ltd. User controlled graphics object movement based on amount of joystick angular rotation and point of view angle
US6002351A (en) * 1995-11-10 1999-12-14 Nintendo Co., Ltd. Joystick device
US6241610B1 (en) 1996-09-20 2001-06-05 Nintendo Co., Ltd. Three-dimensional image processing system having dynamically changing character polygon number
US6346046B2 (en) 1996-09-20 2002-02-12 Nintendo Co., Ltd. Three-dimensional image processing system having dynamically changing character polygon number
US6283857B1 (en) 1996-09-24 2001-09-04 Nintendo Co., Ltd. Three-dimensional image processing apparatus with enhanced automatic and user point of view control

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