JPS6031336A - Frame delay correcting circuit - Google Patents

Abstract

PURPOSE:To operate the system without system-down even at generation of a fault by allowing a loop synchronism control station to cope properly with even >=1 frame of delay in transmission line. CONSTITUTION:An output of a reception control circuit 14 connected to an input signal line 13 is stored in a storage circuit 29 of a loop synchronism control circuit 15 in a loop synchronism control station 1, a storage circuit 30 receives a signal subject to a delay for one loop's share at the storage circuit 29, delayed further by one frame and transmitted to a changeover circuit 28. A delay amount detecting circuit 25 converts the delay of an output signal 23 from a reception timing control circuit 16 to an output signal 24 from a transmission timing control circuit 18 into a pulse signal, a delay bit counter circuit 26 counts the operated delay amount when the pulse signal is logical ''0'' from the detection circuit 25, and a comparator circuit 27 compares the delay amount with a preset bit number. A delay switching circuit 28 receives a signal from the comparator circuit 27 to switch the delay into one-frame delay or 2-frame dalay.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a delay correction circuit that corrects delays in loop data transmission configured by connecting a plurality of terminal stations through a single transmission path.

Conventionally, this type of data transmission system is comprised of one loop synchronization control station that controls the synchronization of a loop-shaped transmission path and a plurality of slave stations. In such a system,
When bypass or loopback control is performed at a certain station, the delay time on the loop transmission path fluctuates, and in some cases, the data change point exactly overlaps with the sampling point, causing a data error and causing the system to go down. For this reason.

As a measure to prevent this, the loop synchronization control station automatically adjusts the transmission path delay to exactly one frame. However, when a failure occurs on a transmission path, even if a system failure is prevented by using loopback or the like, the transmission path delay cannot always be kept within one frame, so there is a drawback that the range of application is limited.

SUMMARY OF THE INVENTION An object of the present invention is to provide an automatic frame delay correction circuit which eliminates the above-mentioned drawbacks.

The delay correction circuit of the present invention includes, in a loop synchronous control station that performs loop synchronous control of a loop data transmission system, a delay amount detection circuit that detects a delay amount between a transmission timing and a reception timing, and a delay amount detection circuit that detects a delay amount between a transmission timing and a reception timing, and a delay amount detection circuit that detects a delay amount between a transmission timing and a reception timing. A comparator circuit that compares the delay amount with the
It is characterized by comprising means for switching between a frame delay and a delay of two or more frames.

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a loop transmission system to which the present invention is applied. In the figure, this system consists of loop synchronous control station 1
and subordinate synchronization stations 2, 3.4. 5-8
Each indicates a terminal device.

9 to 12 each indicate a bypass circuit.

FIG. 2 is a block diagram of the loop synchronous control station 1. In the figure, a reception control circuit 14 connected to an input signal line 13
distributes signals to the terminal reception interface circuit 17. Further, a reception timing control circuit 16 connected to the input signal line 13 reproduces the reception timing signal. The output of the reception timing control circuit 16 is given to the control circuit 14 and the loop synchronization control circuit 15. The output of the control circuit 14 is connected to a loop synchronization control circuit 15 for delay correction and generation of a transmission frame format.

and transfer data. The output of the transmission timing control circuit 18 is supplied to the loop synchronization control circuit 15 and the transmission control circuit 20. The output of the control circuit 15 is connected to the control circuit 20 together with the output of the flag setting circuit 19. The control circuit 20 is connected to the terminal transmission interface circuit 21, inserts data from the terminal device into a frame format, and sends it to the output signal line 13.

FIG. 3 is a circuit block diagram of the automatic delay correction portion of the loop synchronization control circuit 15.

In the figure, a storage circuit 29 stores the output signal from the control circuit 14 and supplies it to the next stage storage circuit 30 and delay switching circuit 28, respectively. The memory circuit 30 receives the signal delayed by 1 frame in the memory circuit 29 and further delays it by 1 frame.
A signal delayed by two frames is sent to the switching circuit 28.

The delay amount detection circuit 25 converts how much the output signal 23 from the reception timing control circuit 16 is delayed with respect to the output signal 24 from the transmission timing control circuit 18 into a pulse signal and sends it to the delay pit counter circuit 26. . The delay pit counter circuit 26 operates when the pulse signal from the detection circuit 25 is '0', counts how many bits the delay amount corresponds to, and sends the output to the comparison circuit 27.
Send to. The comparison circuit 27 is a circuit that receives the signal from the counter 26 and compares it with a preset number of bits. For example, if the number of delay bits is less than 80, it will be delayed by one frame, and if it is 96 bits or more, it will be delayed by two frames. The period between 80 and 95 bits is set as an interval in which the previous delay state is maintained. The delay switching circuit 28 receives the signal from the comparison circuit 27 and switches between one frame delay and two frame delay. Note that by changing the number of set bits of the comparison circuit 27, it is possible to cope with a delay of three frames or more.

As described above, the present invention can appropriately cope with a transmission line delay of one frame or more in a loop synchronous control station, and can operate without stopping the system even when a failure occurs.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram to which the present invention is applied. FIG. 2 is a block diagram of a loop synchronization control station used in the present invention, and FIG. 3 is a block diagram showing an embodiment of the present invention. In the figure, ■... Loop synchronous control station, 2 to 4
...Subordinate synchronization station, 5-8...Terminal device, 9-12...Bypass circuit, 13...
Loop transmission line, 14... Reception control circuit, 15.
...Loop synchronization control circuit. 16... Reception timing control circuit, 17...
...Terminal reception interface circuit, 18...
Transmission timing control circuit, 19... Flag setting circuit, 20... Transmission control circuit, 21...
・Terminal transmission interface circuit, 25...Delay amount detection circuit, 26...Delay pit counter circuit, 27...Comparison circuit, 28...Delay switching circuit , 29, 30... Memory circuit.

Claims (1)

[Claims] In a loop synchronous control station that performs loop synchronous control of a loop data transmission system, a delay amount detection circuit that detects the amount of delay between transmission timing and reception timing, and a comparison that compares the amount of delay with a preset amount of delay. 1. A frame delay correction circuit comprising: a circuit; and means for switching between a delay of one frame and a delay of two or more frames in accordance with the output of the comparison circuit.