JPH0370325A - Frame synchronization system - Google Patents

Abstract

PURPOSE:To evade requirement of much time till the execution of resynchronization by switching a transmission circuit after an asynchronizing frame is set at last when the transmission circuit is switched at a frame sender side. CONSTITUTION:A frame transmission section 1 consists of a frame composition circuit 10, a synchronization bit transmission c 11 and an asynchronization frame transmission circuit 12, and a frame reception section 2 consists of a synchronization bit detection circuit 20 and an asynchronization frame detection circuit 21. When the transmission circuits 11, 12 are switched at a frame sender side, the circuits are switched after an asynchronization frame is sent finally. Thus, several frames to detect cut of synchronism at the receiver side are omitted, the detection of a synchronization bit is quickened and the time till resynchronization attended with out of synchronism is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame synchronization method in digital transmission.

[Conventional technology]

Conventionally, in this type of frame synchronization method, a group of bits having a specific pattern, that is, frame synchronization bits, are inserted at a specific position in a pulse train on the transmitting side, and the receiving side detects this pattern and adjusts the frame. It was a method to identify whether synchronization was achieved.

Therefore, in the conventional frame synchronization method, since synchronization information is only available in the time allocated for frame synchronization within one frame, the frame synchronization bits of multiple frames are monitored in consideration of code errors in the transmission path. However, it is determined that synchronization has been lost only when the synchronization bits of multiple frames are abnormal.

[Problem to be solved by the invention]

The conventional frame synchronization method described above monitors the frame synchronization bits of multiple frames and determines that synchronization has been lost only when the synchronization bits of multiple frames are abnormal. Even if the exit path is switched, there is a disadvantage that it takes at least several frames to detect the out-of-synchronization, even though the out-of-synchronization is actually out, and it takes time until resynchronization is executed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a frame synchronization method that eliminates the above-mentioned drawbacks.

[Means to solve the problem]

The frame synchronization method of the present invention includes a synchronization bit sending circuit that sends out synchronization bits, an asynchronous frame sending out path that creates a frame to quickly bring the other side's receiving circuit into an asynchronous state, and a normal frame synchronization method based on data and synchronization bits. There is a frame transmitting section consisting of a frame assembly circuit that creates a synchronous frame and switches between sending a normal synchronous frame and sending an asynchronous frame under external control, and a frame sending section that detects the synchronous bit of the received frame. It has a frame receiving section composed of a synchronization bit detection circuit that synchronizes frames, and an asynchronous frame detection circuit that controls the synchronization bit detection circuit to an asynchronous state when an asynchronous frame is received during synchronization.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, a frame sending unit l includes a frame assembly circuit 10. The frame receiving section 2 is composed of a synchronous bit sending circuit 11 and an asynchronous frame sending circuit 12, and a synchronous bit detecting circuit 20 and an asynchronous frame detecting circuit 21.

FIG. 2 is a format diagram showing an example of a frame structure transmitted to a transmission path. In Figure 2, a synchronous frame has a synchronous bit F followed by data, and an asynchronous frame has a synchronous bit F, followed by an asynchronous pattern, and a synchronous bit F-F at the high (H) level of the frame synchronous signal.
Place.

Next, the operation of this embodiment will be explained.

First, the frame sending unit 1 sends out a synchronous frame or an asynchronous frame shown in FIG. 2 in accordance with the frame switching control signal 102 in the frame assembling circuit 10. When the frame switching control signal 102 is an instruction to transmit a synchronization frame, the synchronization bit F is transmitted from the synchronization bit transmission circuit 11 when the frame synchronization signal shown in FIG. 2 given to the frame synchronization signal 101 is at "H" level. Ru. In the frame assembling circuit 10, according to the frame synchronization signal 101, the frame synchronization signal F from the synchronization bit sending circuit 11 is switched when it is at the "H" level, and to the I sending data signal 100 when it is at the low ("L") level, as shown in FIG. The synchronization frame shown is assembled and sent out as a frame sending signal 103.

The frame switching signal 102 is a frame sending signal 1 when the frame assembling circuit 10 selects to send an asynchronous frame.
Sent as 03.

When switching is performed under the control of the frame switching signal 102, the frame assembling circuit 10 controls switching at the beginning of the frame in accordance with the frame synchronization signal 101 in order to maintain continuity in frame units, that is, to prevent switching in the middle of the frame. The synchronous bit sending circuit 11 and the asynchronous frame sending circuit 12 all perform frame assembly and switching in synchronization.

Next, the operation of the frame receiving section 2 will be explained.

and perform synchronous pull-in. At this time, if the data happens to have the same pattern as the synchronization bit, there is a possibility of erroneous synchronization, so the synchronization bits of multiple frames are monitored to pull in synchronization. At the stage when synchronization pull-in is completed, a frame synchronization signal shown in FIG. 2 is output, and a synchronization state signal indicating a synchronization state is output.

When the received data is interrupted by 2000 Å, the synchronization bit detection circuit 20 determines that the synchronization has been lost because the synchronization bits do not match.However, considering bit errors on the line, if there are multiple frame errors, the synchronization bit detection circuit 20 determines that the synchronization has been lost. judge. At this time,
A synchronous state signal 202 indicating an asynchronous state is output.

The asynchronous frame detection circuit 21 operates when the synchronous state signal 201 is in the synchronous state, detects an asynchronous frame of the received data signal in synchronization with the frame synchronous signal, and when an asynchronous frame is received, outputs the asynchronous state detection information 203. The signal is output to force the synchronous bit detection circuit 20 into an asynchronous state.

For the asynchronous frame shown in Figure 2, the complement of the synchronous beep F is used to identify that it is not a synchronous frame, but it is also used to distinguish it from a normal synchronous bit error caused by a line error. Therefore, by creating an asynchronous pattern specifically defined for asynchronous use in the data area, consideration is given to preventing erroneous judgments due to line errors.

That is, in this embodiment, in a normal synchronous frame position, an asynchronous frame newly defines a frame in which a bit corresponding to a synchronous bit is used as the complement of a synchronous bit in a synchronous frame to form a specific pattern as an asynchronous pattern at a data position. At the same time, a mechanism is included to immediately change the state to an asynchronous state when an asynchronous frame is received while the received frames are synchronized.

Therefore, when the frame sending side switches the sending circuit,
When switching after sending the last asynchronous frame,
On the receiving side, an asynchronous state can be created immediately upon reception of an asynchronous frame.

〔Effect of the invention〕

As explained above, in the present invention, when switching the transmission circuit on the frame transmitting side, by transmitting an asynchronous frame last and then switching, it is possible to omit several frames for detecting synchronization loss on the receiving side. This has the effect of speeding up the detection of synchronization bits and shortening the time required to resynchronize when synchronization is lost.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the frame synchronization method of the present invention, and FIG. 2 is a frame format diagram showing an example of the transmission signal of FIG. 1. DESCRIPTION OF SYMBOLS 1... Frame sending unit, 2... Frame receiving unit, 10... Frame assembly circuit, 11
... Synchronous bit sending circuit, 12 ... Asynchronous frame sending circuit, 20 ... Synchronous bit detection circuit, 21 ... Asynchronous frame detection circuit.

Claims (1)

[Claims] A synchronous bit sending circuit that sends out synchronous bits, an asynchronous frame sending circuit that creates a frame to quickly bring the receiving device on the other side into an asynchronous state, and a synchronous frame sending circuit that creates a normal synchronous frame from data and synchronous bits and transmits external signals. A frame sending unit consisting of a frame assembly circuit that controls whether to send a normal synchronous frame or an asynchronous frame, and a synchronous bit detection circuit that detects the synchronous bit of the received frame and synchronizes the frame. , and a frame receiving section comprising an asynchronous frame detection circuit that controls a synchronous bit detection circuit to an asynchronous state when an asynchronous frame is received during synchronization.