JPH08139742A - Multiplex transmission device - Google Patents

Abstract

PURPOSE: To improve reliability of a multiplex transmission device by attaining the reception of a reception answer signal despite occurrence of such a fault that cuts a transmission line because an OR of outputs of the comparator devices is outputted from a logical synthesizer device if no reception answer signal is received. CONSTITUTION: The AND gates 26b to 28b output the ANDs of outputs of comparators 23 to 25 and the outputs or counter parts 26a to 28a to a logical synthesizer circuit 29. An OR gate 29a outputs an OR of inputs of those comparators and counter parts to an AND gate 29c. At the same time, the outputs of AND gates 27b and 28b are inputted to an OR gate 29b. The gate 29b outputs an OR of both gates 27b and 28b to the gate 29c. Then the outputs of the gates 29b and 29c are inputted to an OR gate 29d, ana the gate 29d outputs an OR of the inputs of both gates 29b and 29c to a communication control circuit 30. The circuit 30 fetches the output of the gate 29d and controls the application equipment connected together in response to the data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplex transmission device for detecting signals that are multiplex-transmitted on a transmission line.

[0002]

2. Description of the Related Art Conventionally, this type of multiplex transmission device has a CS
MA / CD (Carrier Sense Multiple Access / Collision)
There is a method of using a detection method and returning a reception response bit to a reception response signal area in the data frame when the receiving device normally receives the data frame. Furthermore, in the above device, using the NRZ code,
When communication is performed in baseband, the logic is at a high level (hereinafter referred to as “H”) or a low level (hereinafter referred to as “H”).
It is called "" L "". ) Is continued for many bits, the bit synchronization between the devices will shift, so the bit stuff rule is used. That is, according to the above-mentioned bit stuffing rule, when the logic "H" continues for a certain length of time, the bit stuffing of the logic "L" continues, and when the logic "L" continues for a certain length of time, the logic "H".
There was a thing to insert the bit stuff of and synchronize at the edge of this bit stuff.

An example of such a multiplex transmission device is described in Japanese Patent Application No. 4-182160. In the above multiplex transmission device, when one of the two transmission lines fails,
The logic synthesis circuit selects the failure communication mode in which the logical sum of each comparator is the received data, and outputs the received data to the multiplex transmission control circuit to enable reception even when the transmission line fails. .

[0004]

However, in a system provided with the above-mentioned multiplex transmission device, for example, the multiplex transmission device on the receiving side is connected to the main line via a branch line, and one of the branch lines is disconnected while the other is connected. When performing data transmission with the transmitting-side multiplex transmission device, the receiving-side multiplex transmission device can detect the failure of the transmission path and receive the data in the failure communication mode.
After that, the reception response signal is transmitted, but the transmission side multiplex transmission device cannot detect the failure of the transmission line (branch line in this case). Therefore, in the transmitting side multiplex transmission device, since the reception response signal is transmitted only from one transmission line and cannot be received in the normal communication mode, data retransmission is repeated, and the traffic amount on the transmission line increases. There was a problem.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a multiplex transmission apparatus capable of receiving a reception response signal even if a failure such as disconnection of a transmission line occurs. And

[0006]

In order to achieve the above object, according to the present invention, signals of the transmission lines are connected to each other via at least two common transmission lines (including branch lines). A potential converting means for converting into a predetermined potential, a first comparing means (comparator) for comparing the converted potentials of the respective transmission lines, a converted potential of one of the transmission lines and a predetermined reference potential. The second comparison means (comparator) for comparison, the third comparison means (comparator) for comparing the converted potential of the other transmission line with a predetermined reference voltage, and the output of each of the comparators are logical. In the multiplex transmission apparatus having a logic synthesizing unit (logic synthesizing circuit) for synthesizing and a communication control unit (communication control circuit) for receiving a synthesis result of the logic synthesizing circuit, the communication control The circuit did not receive the reception response signal. Expediently, multiplex transmission apparatus for transmitting a logical sum of the output of each comparator from the logic composition circuit is provided.

[0007]

When the reception response signal cannot be received even though the data is normally received from the transmission line, the communication mode is forcibly changed to the logical sum of the outputs from the comparators. This enables reception of the reception response signal.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a multiplex transmission apparatus according to the present invention will be described below with reference to the drawings of FIGS. FIG. 1 is a configuration block diagram showing a first embodiment of the configuration of a multiplex transmission device according to the present invention. In the figure, since the multiplex transmission devices 20, 40, 41 according to the present invention have the same configuration, the multiplex transmission device 20 will be described as a representative here.

In the multiplex transmission device 20, two transmission lines 1
0 and 11 via branch lines 12 and 13 to a potential conversion circuit 21,
22 is connected, and three comparators 23 to 25 are connected to the potential conversion circuits 21 and 22. The potential conversion circuit 21 converts the signal on the transmission line 10 into a predetermined potential Va, and the potential conversion circuit 22 converts the signal on the transmission line 11 into a predetermined potential Vb. Further, the comparator 23 compares the voltages Va and Vb from both transmission lines 10 and 11, and the comparator 24 compares the voltage Va from the transmission line 10 with a preset reference voltage Vc. The comparator 25 compares the voltage Vb from the transmission line 11 with a preset reference voltage Vd.

The outputs of the comparators 23 to 25 are input to the output control circuits 26 to 28, respectively. Output control circuit 2
6, 27 and 28 are counter units 26a and 27, respectively.
a, 28a and AND gates 26b, 27b, 28b. The outputs of the comparators 23 to 25 are the counter units 26a to 28a and the AND gates 26b to 2, respectively.
8b and the counter units 26a to 28a.
Detects whether the outputs of the comparators 23 to 25 are in the "H" state for a certain period of time, that is, the longest data that can be considered in the data frame or more, for example, T1 time or more. , "H" is output, and "L" is normally output. The outputs of the counter units 26a to 28a are inverted and AND gates 26b to 28b, respectively.
And the logic synthesis circuit 29. The time T1 is the same as the counter units 26a-28.
It may be different for each a.

The AND gates 26b to 28b are provided for the comparator 2.
The logical product of the outputs of 3 to 25 and the outputs of the counter units 26a to 28a is output to the logic synthesis circuit 29. The logic synthesizing circuit 29 is composed of OR gates 29a, 29b, 29d and an AND gate 29c. OR gate 29
The outputs of the counter units 26a to 28a are input to a, and the control signal from the communication control circuit 30 described later is input to the a. The OR gate 29a outputs the logical sum of these inputs to the AND gate 29c. ing. Further, the OR gate 29b includes AND gates 27b and 28.
The output of each b is input, and the OR gate 29b
Outputs the logical sum of these inputs to the AND gate 29c.

The AND gate 29c is the OR gate 2.
The logical product of the outputs of 9a and 29b is output to the OR gate 29d. In addition to the output of the AND gate 29c, the output of the AND gate 26b is input to the OR gate 29d, and the OR gate 29d outputs the logical sum of these inputs to the communication control circuit 30. When the communication control circuit 30 takes in the output (received data) of the OR gate 29d, it controls each application device (not shown) connected according to the data. Further, when the communication control circuit 30 is a transmission node, the communication control circuit 30 controls the transmission circuit 31 to transmit a data frame as shown in FIG. 2 and fetch a reception response signal from each multiplex transmission device. Checking whether the data communication is performed normally. Then, when the reception response signal from any of the multiplex transmission devices cannot be received, the communication control circuit 30 outputs a control signal to the OR gate 29a to open the AND gate 29c and open the comparator 23. ~ 2
The logical sum of the outputs of 5 is taken in as the received signal m from the logic synthesis circuit 29.

The above data frame is shown in FIG.
As shown in, SOF (Start
Of Frame), a priority (PRI) for determining the priority when a plurality of multiplex transmission devices simultaneously transmit data frames to a transmission line, and each subsequent data (DA
TA), a control data area (CONT) that contains data indicating the data length, DATA that is a data area of the length (variable length) indicated by CONT, and CRC of the error check code. , EOD (End Of Data) indicating the end of data, and a reception response signal area of, for example, 12 bits for all the multiplex transmission devices in the system to return the reception response signal in bit correspondence, and the end of the data frame. EOF (End Of Fram)
e) consists of

Here, for example, as shown in FIG. 2, when the multiplex transmission device 20 is a transmission node, the data frame transmitted from the transmission circuit 31 is the multiplex transmission devices 40 and 41.
If both are normally received, the multiplex transmission device 40
Indicates that the multiplex transmission device 41 transmits the reception response signal to the third bit of the reception response signal area, and the multiplex transmission device 41 transmits the reception response signal to the fifth bit of the reception response signal area (see FIGS. 2C and 2D). The multiplex transmission device 20 receives the reception response signals of the multiplex transmission devices 40 and 41 (see FIG. 2B) and confirms that the communication is normally performed.

The first bit of the reception response signal area is the reception response signal transmitted by the multiplex transmission device 20. Next, the frame communication operation of the multiplex transmission device shown in FIG. 1 will be described. Here, the normal signal states of the transmission lines 10 and 11 have a waveform of a passive state and a dominant state as shown in FIG. The passive state is a state in which there is no signal on the transmission line, "L" is expected at the output m of the logic synthesis circuit 29, and the dominant state is a state on the transmission line at which "H" is expected at the output m. I mean. Transmission line 1
The signals 0 and 11 are output potential V in each state as shown in FIG. 2B by the potential conversion circuits 21 and 22.
converted to a, Vb. Also, the output potentials Va and Vb when the transmission lines 10 and 11 are broken are as shown by the alternate long and short dash lines.

Each state of the transmission lines 10 and 11 and the comparators 23 to
The relationship of the outputs of 25 is as shown in Table 1.

[0017]

[Table 1] Here, the converted potentials Va and Vb in the normal state where there is no failure in the transmission lines 10 and 11 are as shown in FIG. 3B, and the outputs of the comparators 23 to 25 in the passive state are shown in Table 1. As shown in the normal communication mode, each becomes "L", and the outputs of the respective comparators 23 to 25 at the time of dominant become "H". The outputs of the comparators 23 to 25 at the time of disconnection failure are as shown in the failure communication mode of Table 1.

In the normal communication mode, the transmission lines 10 and 11
3A is transmitted to each of the comparators 23 to 25, and the signals are converted into potentials as shown in FIG. 3B by the potential conversion circuits 21 and 22 and input to the comparators 23 to 25. Has been done. As shown in Table 1, the outputs of the comparators 23 to 25 are in the "L" state in the passive state and in the "H" state in the dominant state (see FIGS. 3C to 3E). Further, when the transmission lines 10 and 11 are in a normal state, there is no continuous "H" signal for the time T1 or more. Therefore, the counter units 26a to 28a output "L", the AND gates 26b to 28b are opened by the above outputs, and the respective outputs of the comparators 23 to 25 are output.

However, since the outputs of the counter units 26a to 28a are "L" and the control signal from the communication control circuit 30 is usually "L" output, the output of the OR gate 29a is "L". Become. Therefore, AND gate 29c
Is closed, and only the output of the comparator 23 passes through the OR gate 29d and is input as the received signal m to the communication control circuit 30 to perform data communication.

On the other hand, in the present embodiment, as shown in FIG. 1, for example, the branch lines 14 connected to the transmission lines 10 and 11,
It is assumed that the branch communication line 15 is disconnected by the cross mark, and the signal transmitted from the multiplex transmission device 20 is received by the multiplex transmission device 41 in the failure communication mode. In this case,
The signals on the branch lines 14 and 15 have a potential as shown in FIG. This signal is converted into potentials as shown in FIG. 4B by the potential conversion circuits 21 and 22 of the multiplex transmission device 41 and input to the comparators 23 to 25. As shown in Table 1, the outputs of the comparators 23 and 24 are "L" in the passive state and "H" in the dominant state.
This is the state (see FIGS. 4 (c) and 4 (d)). However, since the potential Vb becomes lower than the reference potential Vd due to the disconnection as shown in FIG.
Regardless of whether the signals on 4 and 15 are in the passive state or the dominant state, they are always in the "H" state (Fig. 4).
(E)). Therefore, the counter unit 28a is "H".
Is output, the AND gate 28b is closed. Further, the output of the OR gate 29a becomes "H" by the output of "H" from the counter unit 28a, and the AND gate 29c is opened. Therefore, each comparator 23-2
The logical sum of the outputs of 5 is output from the OR gate 29d.
When the communication control circuit 30 of the multiplex transmission device 41 receives the signal m from the OR gate 29d, the multiplex transmission device 20
A reception response signal is transmitted from the transmission circuit 31 to the.

However, in the multiplex transmission device 20, since the transmitted signal is also received by the device itself, even if a disconnection failure of the branch line 15 occurs, the disconnection failure cannot be detected and the above-mentioned signal in the normal communication mode is detected. Are being received. However, the reception response signal transmitted from the multiplex transmission device 41 is transmitted only through the transmission line 10 because the branch line 15 is disconnected. Therefore, the potentials Va and Vb of the signals on the transmission lines 10 and 11 converted by the potential conversion circuits 21 and 22 of the multiplex transmission device 20 are as shown in FIG. , The output of the comparator 23 in the normal communication mode is selected as the reception signal m. Therefore, in the comparator 23,
As shown in FIG. 5B, the reception response signal from the multiplex transmission device 41 cannot be detected.

The communication control circuit 30 of the multiplex transmission device 20 is
When it is detected that there is no reception response signal of the multiplex transmission device 41 at a predetermined position in the reception response signal area of the data frame, the control signal in the "H" state is output and the AND gate 29c is opened. Then, the failure communication mode in which the logical sum of the comparators 23 to 25 is used as the reception signal m is forcibly selected, and the same data frame is transmitted again.

When the multiplex transmission apparatus 41 receives this retransmitted data frame and returns a reception response signal, the multiplex transmission apparatus 20 has a control signal of "H". The logical sum of the comparators 23 to 25 is fetched as the received signal m. Since a normal signal is output from the comparator 25 of the comparators 23 to 25, the reception response signal of the multiplex transmission device 41 is received, and the communication control circuit 30 normally performs data communication. You can recognize that.

On the other hand, even when the data frame is retransmitted in the failure communication mode, if the reception response signal of the multiplex transmission device 41 is not received, the multiplex transmission device 20 is received.
Determines that the multiplex transmission device 41 is out of order, the communication control circuit 30 outputs a control signal in the "L" state, switches from the failed communication mode to the normal communication mode, and returns to the original state. After that, data communication is performed assuming that there is no multiplex transmission device 41. That is, even if the reception response signal of the multiplex transmission device 41 is not received, the multiplex transmission device 20 does not retransmit the data frame,
Ignore and perform data communication.

Therefore, in this embodiment, if the reception response signal from another multiplex transmission device is not received, the communication mode can be forcibly switched to the failure communication mode, so that the data retransmission is repeated. As a result, it is possible to receive the reception response signal and prevent an increase in the traffic amount on the transmission path.

[0026]

As described above, according to the present invention, the potential conversion means is connected to each other through at least two common transmission lines, and converts the signal of the transmission lines into a predetermined potential. A first comparing the electric potentials of the converted transmission lines;
Comparing means for comparing the electric potential of the one converted transmission line with a predetermined reference potential, and third comparing means for comparing the electric potential of the other converted transmission line with a predetermined reference voltage. In the multiplex transmission apparatus using a reception response signal, and a logic synthesizing means for logically synthesizing the outputs of the respective comparing means, and a communication control means for receiving the synthesis result of the logic synthesizing means. When the reception response signal is not received, the communication control means causes the logic synthesis means to send out the logical sum of the outputs of the comparison means, so that a failure such as disconnection of the transmission line occurs. However, the reception response signal can be received, and the reliability of the multiplex transmission device can be improved.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of a multiplex transmission device according to the present invention.

FIG. 2 is a diagram showing an example of a data frame transmitted by the multiplex transmission device shown in FIG.

FIG. 3 is a diagram showing potentials in a transmission line and respective parts of a multiplex transmission device in a normal state.

FIG. 4 is a diagram showing potentials at a branch line and each part of a receiving side multiplex transmission device when the branch line is broken.

FIG. 5 is a diagram showing a potential at each part of the transmission-side multiplex transmission device when a branch line is broken.

[Explanation of symbols]

 10, 11 Transmission line 12-15 Branch line 20, 40, 41 Multiplex transmission device 21, 22 Potential conversion circuit 23-25 Comparator 26-28 Output control circuit 26a-28a Counter unit 26b-28b, 29c AND gate 29 Logic combination circuit 29a, 29b, 29d OR gate 30 communication control circuit 31 transmission circuit

Claims (2)

[Claims] 1. A potential conversion means that is connected to each other through at least two common transmission lines and that converts a signal of the transmission line into a predetermined potential, and the converted potentials of the respective transmission lines. The first comparing means for comparing, the second comparing means for comparing the converted potential of the one transmission path with a predetermined reference potential, and the second comparing means for comparing the converted potential of the other transmission path with the predetermined reference voltage. A third comparison means for comparing, a logic synthesizing means for logically synthesizing the outputs of the respective comparing means, and a communication control means for receiving the synthesis result of the logic synthesizing means, and multiplexing using a reception response signal In the transmission device, the communication control means causes the logic synthesis means to send out a logical sum of outputs of the comparison means when the reception response signal is not received. 2. The multiplex transmission device according to claim 1, wherein the multiplex transmission device is connected to the transmission line via a branch line.