JP2689857B2 - High-speed digital leased line alarm transfer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an I terminator (I-DS).
The present invention relates to a method of transferring 64K line fault information between devices to a CNE through a high-speed digital leased line used when multi-stage relay connection of a line from U) with an I interface line extension device.

[0002]

2. Description of the Related Art Generally, as a transfer method (alarm transfer method) of this type, for example, a network test method described in Japanese Patent Laid-Open No. 2-2785 is known.

Here, referring to FIG. 3, each of the (N-1) th stage, the Nth stage, and the (N + 1) th stage I interface line extension device has the frame structure shown in FIG.
Connected to each other with 3M signals. In FIG. 4, ◯ indicates transfer of an alarm or transfer of a calculation result, and ● indicates detection of an alarm.

Here, the transfer of the 64k line alarm between the I interface line extension devices will be outlined for each alarm.

The 64k parity transmitted from the (N-1) th stage I interface line extension device is the Ith stage of the Nth stage.
It is not detected on the receiving side of the interface line extension device, or even if it is detected, the alarm is not transferred. The N-th stage I interface line extension device performs a parity operation in units of 64k lines, inserts the operation result into a bit in the 6.3M signal frame, and sends it to the (N + 1) th stage I interface line extension device.

When an error occurs in the transmission line between the (N-1) th stage I interface line extension device and the Nth stage I interface line extension device, the Nth stage I interface line extension device generates 6.3M. A CRC error is detected, and an error is forcibly inserted for 64k parity of all 64k lines accommodated in the relevant 6.3M line (N
+1) It is sent to the I interface line extension device at the stage.

Next, the 64 kBERR (code error detection notification signal) transmitted from the (N + 1) th stage I interface line extension device is not detected or detected on the receiving side of the Nth stage I interface line extension device. However, the alarm is not sent. When 6.3 MBERR is detected by the N-th stage I interface line extension device, the 6.3 M
The 64kBERR bits of all 64k lines accommodated in the line are sent to the (N + 1) th stage I interface line extension device as an alarm. On the other hand, 6.3MBERR
If is not detected, it is sent without alarm.

The 64K AIS sent from the (N-1) th stage I interface line extension device is not detected at the receiving side of the Nth stage I interface line extension device, or no alarm is issued even if it is detected. In the Nth stage I interface line extension device, the 64kAIS bits of all 64k lines accommodated in the 6.3M line are fixed to the state without alarm and sent to the (N + 1) th stage I interface line extension device. .

[0009]

In the case of the above-mentioned alarm transfer, 64 k transmitted from the (N-1) th stage I interface line extension device, even though it is a relay line.
64k with parity, 64kBERR, and 64kAIS
There is a problem that the line alarm is not transferred to the I interface line extension device in the Nth stage and thereafter.

The object of the present invention is to transfer the 64k parity, 64kBERR, and 64kAIS 64k line alarm sent from the (N-1) th stage I interface line extender to the I interface line extender after the Nth stage. To provide a transfer method.

[0011]

According to the present invention, a plurality of I interface line extension devices are used for transmission control of a high-speed digital leased line which is multistage relay-connected by a 6.3M line, and is connected to the 6.3M line. Stores 64k lines,
An identification signal indicating whether or not the 6.3M line is a relay line is inserted in the spare bit of the 6.3M signal, and each of the I interface line extension devices has the 6.
First means for detecting a fault in the 6.3M line in response to a 3M signal and generating first information indicating the presence / absence of a fault; and detecting a fault for each 64k line in response to the 6.3M signal Second means for generating second information indicating the presence / absence of a failure for each of the 64k lines, and third means for taking the logical sum of the first and second information to generate a logical sum result. When,
Selecting means for selecting the logical sum result as selection information when the identification signal represents the trunk line, and selecting the first information as the selection information when the identification signal does not represent the trunk line; Fourth means for performing a line check for each of the 64k lines to generate a self-device check result, and if the selection information has a first value, the self-device check result is forcibly made into error information and used as alarm information. Fifth means for sending out the self-device check result as the alarm information when the selection information has a second value, and multiplexing means for multiplexing and sending the 6.3M signal and the alarm information It is possible to obtain an alarm transfer system for a high-speed digital leased line characterized by being equipped with.

[0012]

Next, the present invention will be described by way of examples.

Referring to FIG. 1, the (N-1) th stage, the Nth stage, and the (N + 1) th stage I interface line extenders are connected to each other by a 6.3M signal having the frame structure shown in FIG. For example, an I terminator (not shown) is arranged at the front side of the (N-1) th stage I interface line extension device, and a rear side of the (N + 1) th stage I interface line extension device. CNE (not shown)
Is arranged. In the present invention, the spare bit in the 6.3M frame structure shown in FIG. 4 is used as a signal for identifying whether or not the 6.3M line is a relay line. here,
When it is a trunk line, it is set to "0", and when it is not a trunk line, it is set to "1".

Referring also to FIG. 2, first, the N-th stage I interface line extension device receiver will be described.

The 6.3M signal (main signal) input to the N-th stage is subjected to synchronization detection by the 6.3M frame synchronization detection unit 1 and the frame synchronization of the 6.3M signal is established. 6.3M
The CRC error detector 2 receives the 6.3M signal and
Is performed to detect a 6.3M transmission line error between the devices. Then, in the 6.3 MCRC error detection unit 2, "1" is set when there is an error, and "0" when there is no error.
Is applied to the 1A input of the selector 11 and the OR circuit 9.

The 6.3MBERR detector 3 receives the 6.3M signal and detects the presence or absence of the BERR bit in the 6.3M frame structure. Then, in the 6.3MBERR detection unit 3, the selector 1 sets "1" when an alarm is issued and "0" when it is normal.
2A input of 1 and the OR circuit 10.

In the 6.3M spare bit detector 4, 6.3M
Upon receiving the signal, it detects whether the spare bit in the 6.3M frame structure is "0" or "1", and inputs the detection result to the control input S of the selector 11.

In the 64kST frame synchronization detection section 5, 6.
Upon receiving the 3M signal, synchronization of the 64kST frame is established.

The 64k parity error detector 6 receives the main signal and performs a parity check in units of 64k lines.
Detect 4k line error. Then, the 64k parity error detection unit 6 gives "1" to the OR circuit 9 when there is an error and "0" when there is no error. The OR circuit 9 takes the logical sum of the detection result from the 6.3MCRC error detection unit 2 and the detection result from the 64k parity error detection unit 6 and applies it to the 1B input of the selector 11.

The 64 kAIS detector 7 receives the main signal,
64kAIS is detected in units of 64k lines, and "1" is given to the 2B input of the selector 11 at the time of alarm and "0" at the time of normal. The 2A input of the selector 11 is "0"
Fixed to

The 64 kBERR detector 8 receives the main signal and detects the presence or absence of the BERR bit in the ST frame structure. As a result, the 64 kBERR detection unit 8 inputs "1" to the OR circuit 10 at the time of alarm and "0" at the time of normal. Then, the OR circuit 10 takes the logical sum of the detection result from the 6.3 MBERR detection unit 3 and the detection result from the 64 kBERR detection unit 8 and outputs the result as the 3B of the selector 11.
Give to input.

When the detection result of the 6.3M spare bit detection unit 4 is "0", that is, when this 6.3M line is a relay line, the selector 11 selects 1B, 2B, and 3.
B input is selected and output from 1Y, 2Y, and 3Y outputs, respectively. On the other hand, when the detection result of the 6.3M spare bit detection unit 4 is “1”, that is, this 6.3M
If the line is not a trunk line, the selector 11 has 1A, 2A,
And 3A input to select 1Y, 2Y, and 3Y respectively
Output from output.

In the 64k parity operation unit 12, 64kST
When the 64kST signal from the frame synchronization detector 5 is received, 6
Parity calculation is performed in units of 4k lines. Then, the calculation result is given to the error insertion unit 13. When the 1Y output of the selector 11 is "1", the error insertion unit 13 forcibly gives the operation result of the 64k parity operation unit 12 to the multiplexing unit 16 as "error". On the other hand, in the error insertion unit 13, when the 1Y output of the selector 11 is “0”, the operation result of the 64k parity operation unit 12 is given to the multiplexing unit 16 as it is.

In the 64 kAIS insertion section 14, the selector 11
When the 2Y output of “1” is 64kAI of the corresponding 64k line
Set S as "alarm" and 2Y output is "0". Applicable 6
The 64kAIS of the 4k line is given to the multiplexing unit 16 as "no alarm".

In the 64 kBERR insertion unit 14, the selector 1
When the 3Y output of 1 is “1”, 64kB of the corresponding 64k line
When the ERR is “alarm present” and the 3Y output is “0”, the 64 kBERR of the corresponding 64 k line is given to the multiplexing unit 16 as “no alarm”.

The multiplexer 16 multiplexes the main signal, 64k parity, 64kAIS, and 64kBERR into a multiplexed signal.

Referring again to FIG. 1, the (N-1) th stage I
A 64k line between I interface line extension devices when the spare bit in the 6.3M signal is "0" and a 6.3M signal is sent from the interface line extension device, that is, when the 6.3M line is a trunk line The transfer of alarms will be described for each alarm.

In the N-th stage I interface line extension device, a parity operation is normally performed in units of 64k lines, and the operation result 24 is inserted into a bit in the 6.3M signal frame to insert the (N + 1) th stage I interface. Send to the line extension device. In the N-th stage I interface line extension device, when the calculation result 23 obtained by calculating the 64k parity sent from the (N−1) th stage I interface line extension device is an error, the calculation result 24 is obtained for the 64k line. The error insertion unit 28 forcibly inserts an error and sends it out.

When an error occurs in the inter-device transmission line between the (N-1) th stage I interface line extension device and the Nth stage I interface line extension device, the Nth stage I interface line extension device , 6.3M CRC error 22 is detected, and an error is forcibly inserted into the calculation result 24 for all 64k lines accommodated in the corresponding 6.3M line and transmitted. Then, in the N-th stage I interface line extension device, the BERR is sent to the (N + 1) th stage I interface line extension device as it is for the corresponding 64k line.

When 6.3 MBERR 25 is detected in the N-th stage I interface line extension device, the N-th stage I interface line extension device detects that 6.3 MBERR25.
The 64kBERR bits of all 64k lines accommodated in the line are sent to the (N + 1) th stage I interface line extension device as an alarm. Then, in the N-th stage I interface line extension device, the AIS is sent to the (N + 1) th stage I interface line extension device as it is for the corresponding 64k line.

When the spare bit in the 6.3M signal is sent out as "1" from the (N-1) th stage I interface line extension device, that is, when the 6.3M line is not a relay line, The transfer of the 64k line alarm between the I interface line extension devices is the same as the example shown in FIG.

[0032]

As described above, according to the present invention, in a high-speed digital line connected in multiple stages by using a plurality of I interface line extension devices, a line is a relay line using spare bits in a 6.3M frame. Since the signal for identifying whether or not to transmit is transmitted, there is an effect that the 64k line alarm transfer can be switched.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an embodiment of an alarm transfer method according to the present invention.

FIG. 2 is a block diagram showing an I interface line extension device receiver to which an embodiment of an alarm transfer method according to the present invention is applied.

FIG. 3 is a block diagram for explaining an example of a conventional alarm transfer method.

FIG. 4 is a diagram for explaining a frame structure of a 6.312 Mb / s signal.

[Explanation of symbols]

 1 6.3M Frame Sync Detection Unit 2 6.3 MCRC Error Detection Unit 3 6.3 MBERR Detection Unit 4 6.3M Spare Bit Detection Unit 5 64kST Frame Synchronization Detection Unit 6 64k Parity Error Detection Unit 7 64kAIS Detection Unit 8 64kBERR Detection Unit 9 , 10 OR circuit 11 selector 12 64k parity operation unit 13 error insertion unit 14 64kAIS insertion unit 15 64kBERR insertion unit 16 multiplexing unit

Claims (1)

(57) [Claims] 1. A plurality of I interface line extension devices are used for transmission control of a high-speed digital leased line connected in multiple stages by a 6.3M line, and the 6.3M line has 6 lines.
4k line is accommodated, the spare bits of 6.3M signal the 6.3M line is inserted an identification signal indicating whether the trunk line, the I interface Line Extender instrumentation
First means for each location to generate a first information indicating whether a failure to detect a failure of the 6.3M line in response to the 6.3M signal, depending on the 6.3M signal 64
Second means for detecting a failure in units of k lines and generating second information indicating the presence or absence of a failure for each of the 64k lines, and a logical sum of the first and the second information. And means for selecting the logical sum result as selection information when the identification signal represents the trunk line and selecting the first information as the selection signal when the identification signal does not represent the trunk line. selecting means for selecting as the selection information, the 64
Fourth means for performing a line check for each k lines to generate a self-device check result, and the selection information is a first value.
And the self-device check result is forcibly converted into error information and alarmed.
If the selection information has a second value, the
The device check result is sent as the alarm information.
An alarm transfer system for a high-speed digital leased line, characterized in that the alarm transfer system comprises the means 5 and a multiplexing means for multiplexing and transmitting the 6.3M signal and the alarm information.