JP2786101B2 - Bus failure detection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus fault detecting system for detecting an intermittent fault before a fixed fault of a loop bus occurs in a multiprocessor system in which a plurality of processors are connected to a loop bus.

[0002]

2. Description of the Related Art A conventional loop bus fault detection method is intended for a fixed fault in which transmission / reception on the bus loop is completely impossible. There are a switching system and a loopback system in which a fixed fault location is separated and a loop is formed using two loops of a duplex bus loop.

However, these conventional bus loop switching systems and loopback systems detect loss of a token frame and physical disconnection of the bus loop, making transmission and reception on the bus loop completely impossible. It was intended for fixed failures and not for intermittent failures before the failure.

For example, in a "loop digital data highway apparatus" described in Japanese Patent Application Laid-Open No. 57-97753, a plurality of data transmission / reception terminal stations and one central control station are connected in a loop by one transmission line. In a loop type digital data highway apparatus for transmitting and receiving digital data, a data transmitting / receiving terminal detects an interruption of an input signal, and an address including its own address immediately according to a command from the input detecting section when there is no input. An address signal generator for transmitting a signal and a register for delaying one or more bits between the received signal and the transmitted signal are provided. The central control station confirms that the received signal is an address signal and transmits the signal. Equipped with an address signal receiving unit that detects the address of the data transmission / reception end station, and passes when an input signal interruption failure occurs By knowing the address of the data transmission / reception terminal that should receive the first signal, the central control station detects that a failure has occurred immediately before this data transmission / reception terminal. Is detected.

[0005]

SUMMARY OF THE INVENTION These conventional methods are:
It is intended for fixed failures where transmission and reception are completely impossible, and not for intermittent failures before reaching the fixed failure. Since both bus loop switching and loopback switching during operation require a switching time,
There was a problem that it had a significant effect on the running system.

An object of the present invention is to provide a bus failure detection method for detecting an intermittent failure before a fixed failure of the loop bus occurs in a multiprocessor system in which a plurality of processors are connected to the loop bus. .

[0007]

According to the present invention, there is provided a bus failure detection system in a multiprocessor system in which a plurality of processors are connected to a loop-shaped bus and communicate with each other using the bus. A token frame reception counter field and a failure information bit field are provided in a token frame that is a loop control right frame, and the master node sets a value obtained by incrementing the token frame reception counter field by +1 each time the token frame is transmitted. Holding means for holding the value of the token frame reception counter field in the received token frame in its own slave node each time the slave node receives the token frame; Receive the frame Each time, the value of the token frame reception counter field of the received token frame is compared with the value obtained by adding +1 to the previous value of the held token frame reception counter field, and when these two values are different, A second transmission means for transmitting a token frame in which failure occurrence mark information is added to a corresponding bit of the own node area of the failure information bit field is provided.

[0008] The master node further comprises a fault detecting means for detecting which processor has an intermittent fault from the fault occurrence mark information in the fault information bit field in the received token frame. Is obtained.

[0009]

Next, the present invention will be described with reference to the drawings.

FIG. 1A is a system block diagram of a bus loop multiprocessor system showing an embodiment of a bus failure detection system according to the present invention, and FIG. 1B is a bus loop control right frame in FIG. FIG. 3 is a frame configuration diagram illustrating an example of a token frame.

Referring to FIG. 1A, a bus loop multiprocessor system according to the present embodiment has a master node (MST) 1 having a bus management processor and a plurality of slave nodes (SL) each having a slave processor.
BA, SLBB, SLBC) 3, 4, and 5 are connected to the bus 2 in a loop.

When detecting a bus failure in a bus loop multiprocessor system, the MST 1 provides a data area in a token frame 6 which is a bus loop control right frame. An information bit field is provided and transmitted to the bus 2. According to the token frame reception counter field and the failure information bit field, the MST1
Can detect a bus failure.

Referring to FIG. 1B, the token frame is composed of a frame synchronization section (FLG) 61, an address section (ADR) 62, a control section (CTL) 63, a data area section (INF) 64, and a frame guarantee section. The data area (INF) 64 includes a token frame reception counter field (CNT) 641 for setting a token frame reception count value, and a failure information bit field (FLT) 64 for setting a failure information bit.
2 is provided.

Next, the operation of this embodiment will be described.

Each time the master node MST1 sends out the token frame 6, the CNT641 sets a value obtained by incrementing +1 and sends it out to the bus 2. Each slave node S
Each time LBA3, SLBB4 and SLBC5 receive the token frame 6, they hold the value of CNT641 internally.

For example, when the token frame 6 in which the value “1” is set in the CNT 641 in the MST 1 is transmitted to the bus 2, the SLBA 3, SLBB 4 and SLBC 5 hold the value “1” in each CNT 641.

In this state, when an intermittent failure 21 occurs between SLBB4 and SLBC5, the MST 1 increments the value previously transmitted to the CNT 641 of the token frame 6 by +1 and sets the value to "2". Bus 2
To send to.

Since SLBA3 and SLBB4 can receive this token frame 6 without any problem, CNT641
Holds the value "2". However, since the SLBC 5 cannot receive the token frame 6 from the MST 1 because the intermittent failure 21 has occurred upstream, the CNT 64
The value of 1 remains "1".

The MST 1 cannot receive a token frame from the bus 2 due to the occurrence of the intermittent failure 21 and, when detecting that the previously transmitted token frame 6 has disappeared, sets the value “3” to the CNT 641. And sends it out to the bus 2 again.

In SLBA3 and SLBB4, this CN
When the token frame 6 in which the value “3” is set in T641 is received, the CNT 641
Is compared with a value obtained by incrementing the previous value “2” held in each CNT 641 by +1 (that is, the value “3”).

Since the comparison results match, SLBA3
And SLBB4 each determine that no intermittent failure has occurred upstream of their own slave node, and
The value “3” is held in the NT 641 and the token frame 6 is transmitted to the downstream slave node.

When the SLBC 5 receives the token frame 6 from the upstream slave node, the value “3” of the CNT 641 of the token frame 6 and the value “1” held in the CNT 641 are incremented by +1 (ie, the value “1”). 2 ").

Since the comparison results do not match, it is detected that the intermittent failure 21 has occurred upstream of the own slave node, the received value "3" is held in the CNT 641, and the own node area of the FLT 642 of the token frame 6a is stored. And sends it to the bus 2.

The MST 1 can detect which of the slave nodes has an intermittent failure based on the node area information of the FLT 642 in the token frame 6a received from the SLBC 5 via the bus 2.
In MST1, the contents of FLT642 are cleared and CNT6
The token frame 6 in which the value “3” of 41 is incremented by +1 and the value “4” is set is transmitted to the bus 2.

By repeating the above operation, in this embodiment, it is possible to detect a place where an intermittent failure occurs in a normal data transmission / reception operation.

[0026]

As described above, the present invention relates to a bus failure detection system in a multiprocessor system in which a plurality of processors are connected to a loop-shaped bus and the processors communicate with each other using the bus. A token frame reception counter field and a failure information bit field are provided in a token frame which is a control right frame, and the master node sets and transmits a value obtained by incrementing the token frame reception counter field by +1 each time a token frame is transmitted. Each time a slave node receives a token frame, the slave node holds the value of the token frame reception counter field in the received token frame inside its own slave node, and the token node holds the value of the token frame reception counter field. If the two values are different by comparing the value obtained by adding +1 to the previous value of the frame reception counter field, a token frame in which the corresponding bit of the own node area of the failure information bit field has failure occurrence mark information is provided to the master node. By transmitting, the location of the intermittent failure before reaching the fixed failure in the loop bus can be detected without affecting the operation system,
It is possible to take an action for the failure at an early stage before the occurrence of the fixed failure, and to perform a stable system operation.

[Brief description of the drawings]

FIG. 1A is a system block diagram of a multiprocessor system showing an embodiment of a bus failure detection method according to the present invention, and FIG. 1B is an example of a token frame which is a bus loop control right frame in FIG. FIG. 3 is a diagram showing a frame configuration.

[Explanation of symbols]

1 Master node (MST) 2 Bus 3, 4, 5 Slave node (SLBA, SLBB,
SLBC) 6, 6a Token frame 21 Intermittent failure 61 Frame synchronization part (FLG) 62 Address part (ADR) 63 Control part (CTL) 64 Data area part (INF) 65 Frame guarantee part (CRC) 641 Token frame reception counter field (CNT) 642 Fault information bit field (FLT)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04L 29/14 H04L 13/00 313

Claims (2)

(57) [Claims] In a bus failure detection method in a multiprocessor system in which a plurality of processors are connected to a loop-shaped bus and communicate with each other using the bus, a token frame as a bus loop control right frame is included in a token frame. A token frame reception counter field and a failure information bit field, and the master node includes first transmission means for setting and transmitting a value obtained by incrementing the token frame reception counter field by +1 each time the token frame is transmitted, Each time the slave node receives the token frame, the slave node holds the value of the token frame reception counter field in the received token frame in its own slave node, and each time the token frame is received, The value of the token frame reception counter field of the frame is compared with a value obtained by adding +1 to the previous value of the held token frame reception counter field. A second transmission unit for transmitting a token frame in which failure occurrence mark information is placed on a corresponding bit of the node area. 2. The system according to claim 1, wherein the master node includes a fault detecting unit for detecting which processor has an intermittent fault from the fault occurrence mark information in the fault information bit field in the received token frame. 2. The bus failure detection method according to claim 1, wherein