JP3352607B2 - Serial bus connection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial bus connection device having a bus connection structure such as a control device in an information processing device or an exchange connected to a serial bus having a small number of signal lines, and more particularly to a high reliability. The present invention relates to a serial bus connection device having a failure propagation preventing means for securing.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional serial bus connection device. In this serial bus connection device, a plurality of (for example, three) functional units 10-1 to 10-3 are connected to a serial bus 1, and these functional units 10-1 to 10-3 are connected via the serial bus 1. Communicable with each other. Serial bus 1
Is a single data line 1-1 and a plurality of (eg, two) data lines for controlling transmission and reception of data on the data line 1-1.
And control lines 1-2 and 1-3. Control line 1
For example, the operation of the control line 1-2 indicates that the serial bus 1 is in use, and the operation of the control line 1-3 is as follows.
Is used to indicate that data is being transmitted to the data line 1-1.

A plurality of functional units 10-1 to 10-3
Is composed of a central processing unit (hereinafter, referred to as “CPU”), a memory, a local area network (hereinafter, referred to as “LAN”) controller, and the like.
From U, the serial bus 1 is used for maintenance control (lamp control) of a memory, a LAN controller, and the like. Each functional unit (for example, 10-1) includes a plurality of receiver elements 11-1 to 11-1 whose input sides are connected to the serial bus 1.
And a plurality of serial bus input lines 12 (for example, one data input line 12-1 and two control input lines 12-2 and 12-3). Thus, a serial bus input control unit 13 is connected. The serial bus input control unit 13 is connected to an internal circuit 14 including a CPU, a memory, a LAN controller, and the like, and the internal circuit 14 is connected to a serial bus output control unit 15. The serial bus input control unit 13 and the serial bus output control unit 15 are connected to the internal circuit 14 to realize the operation in the functional unit 10-1. On the output side of the serial bus output control unit 15, a plurality of serial bus output lines 16 (for example, one data output line 16-1 and two control output lines 16-2, 16-
The input sides of the plurality of open collector driver elements 17-1 to 17-3 are connected through 3), and the output sides of these driver elements 17-1 to 17-3 are connected to the serial bus 1.

In FIG. 2, a signal on the serial bus 1 is shown in a negative polarity (low level is logic 1) based on a general circuit implementation.
The serial bus output line 16 and the serial bus input line 12 are shown with positive polarity (high level is logic 1). The open collector driver elements 17-1 to 17-3 drive their outputs to a low level (logic 1) when this input is at a high level (logic 1). In this case, it has the function of not driving the output.

Next, the operation of the serial bus connection device shown in FIG. 2 will be described. In input from the serial bus 1 in each of the functional units 10-1 to 10-3, signals on three lines 1-1 to 1-3 of the serial bus 1 are converted into three receiver elements 11-1 to 11-11. -3 and serial bus input line 12
Is input to the serial bus input control unit 13 via the.
Thereby, the internal circuit 14 performs a predetermined process. In the functional unit (for example, 10-1), when outputting to the serial bus 1, the serial bus output control units 15 to 3
A signal is output to the serial bus output lines 16, and this signal is output to three open collector driver elements 17-1 to 17-1.
It is output on the serial bus 1 via 7-3. That is, the serial bus output control unit 15 receives the serial bus output request from the internal circuit 14, turns on the serial bus output line 16 in a format and timing suitable for the serial bus protocol, and opens the open collector driver element 17.
The data is transmitted to other functional units 10-2 and 10-3 connected to the serial bus 1 via -1 to 17-3. Here, when the serial bus output line 16 is at a low level (logic 0), the other functional units 10-2 and 10-
3 is not adversely affected, and a signal is transmitted onto the serial bus 1 only when the signal is at a high level.

[0006]

However, in the conventional serial bus connection device, for example, the functional unit 10
In the case where the serial bus output control unit 15 in -1 fails and the functional unit 10-1 continues to output a signal on the serial bus 1, the following inconvenience occurs. When the functional unit 10-1 breaks down and continues to output a signal, the other functional units 10-2 and 10-
3 also becomes impossible. Such a communication failure is particularly problematic in a system that requires high reliability. For example, considering a case where the functional unit 10-1 is a LAN controller, the functional unit 10-2 is a CPU, and the functional unit 10-3 is a memory,
Even though only the LAN controller has failed, the memory cannot be operated, resulting in a catastrophic failure, resulting in a device down. Further, it is difficult to identify the functional unit 10-1 in which the failure has occurred, and there is a problem that it takes time to recover from the failure. SUMMARY OF THE INVENTION It is an object of the present invention to solve the problems of the prior art and to provide a highly reliable serial bus connection device having a failure propagation prevention means.

[0007]

In order to solve the above problems SUMMARY OF THE INVENTION In the present invention, a serial bus consisting of a plurality of signal lines of the several double, connected to said serial bus, each other through the serial bus A serial bus connection device comprising: a plurality of functional units for transmitting and receiving signals; wherein each of the functional units outputs a transmission signal transmitted from the inside through a plurality of output lines to the serial bus. Means, receiving means for receiving a transmission signal sent from the serial bus, and inputting the received signal to the inside through a plurality of input lines, and self-stack detecting means. The self-stack detecting means counts a duration of an output signal output from each of the plurality of output lines.
Means , and if the duration of the output signal is within a predetermined time, the counting means is reset and the output signal is reset.
When the duration of the signal is longer than a predetermined time, the driver means is turned off by the carry signal of the counting means. According to the present invention, since the serial bus connection device is configured as described above, if a situation occurs in which one of the plurality of functional units fails and continues to output a signal on the serial bus, Ri by the self-stack detection means in the functional unit, a plurality of output lines
Of each output signal is measured to detect the failure state, and the output of the signal to the serial bus is stopped.

[0008]

FIG. 1 is a block diagram of a serial bus connection device showing an embodiment of the present invention. This serial bus connection device includes a plurality of (for example, three) functional units 3 including a CPU, a memory, a LAN controller, and the like, which are connected to a serial bus 20 having a small number of signal lines, as in the related art.
0-1 to 30-3 are connected, and these functional units 3
0-1 to 30-3 can communicate with each other via the serial bus 20. As in the conventional case, the serial bus 20 includes one data line 20-1 and a plurality of (for example, two) control lines 20-2 for controlling transmission and reception of data on the data line 20-1. , 20-3. In each functional unit (for example, 30-1),
As in the conventional case, the input side includes three receiver elements 31-1 to 31-3 connected to the serial bus 20, and the output side includes a plurality of serial bus input lines 32 (for example, one data bus). It is connected to the serial bus input control unit 33 via the input line 32-1 and the two control input lines 32-2, 32-3). Serial bus input control unit 33
Is connected to an internal circuit 34 composed of a CPU, a memory, a LAN controller, and the like.
Are connected to the serial bus output control unit 35. The serial bus input control unit 33 and the serial bus output control unit 35 are connected to the internal circuit 34 to realize the operation in the functional unit 30-1.
On the output side of the serial bus output control unit 35, a plurality of serial bus output lines 36 (for example, one data output line 3
6-1 and two control input lines 36-2, 36-3), three two-input open collector driver elements 37
One of the input sides of -1 to 37-3 is connected, and their output sides are connected to the serial bus 20.

This embodiment is different from the conventional one in that
A self-stack detecting means (for example, a self-stack detecting circuit) 40 is connected to the serial bus output line 36 on the output side of the serial bus output control unit 35, and an output enable line connected to the output side of the self-stack detecting circuit 40. 50, three open collector driver elements 37-1
That is, the on / off state of the outputs of ３７37-3 is controlled. The self-stack detection circuit 40
It is detected that any one of the three serial bus output lines 36 continues to output a signal for a certain period of time (a length that is impossible for normal data transmission / reception), and if the output is continued for a certain period of time. For example, this is a circuit that suppresses output to the serial bus 20 by turning off the output enable line 50 connected to the open collector driver elements 37-1 to 37-3.

FIG. 3 shows the self-stack detecting circuit 4 shown in FIG.
FIG. 4 is a circuit diagram illustrating a configuration example of a 0. This self-stack detection circuit 40 has three input terminals 36
And an output terminal thereof is connected to one input terminal of a two-input AND element 42 and an input terminal of an inverter element 43 for signal inversion. The output terminal of the AND element 42 is connected to the enable terminal E of the counter 44, and the reset terminal R of the counter 44 is connected to the output terminal of the inverter element 43. The carry terminal C of the counter 44 is connected to an input terminal of an inverter element 45 for signal inversion, and an output terminal of the inverter element 45 is connected to an output enable line 50. The output enable line 50 is connected to the AND element 42.
And the other input terminals of the three 2-input open collector driver elements 37-1 to 37-3.

Next, (A) the input operation from the serial bus 20 of the device shown in FIGS.
The output operation to the device will be described. (A) Input operation from serial bus 20 Each functional unit 30-1 to 30 from serial bus 20
-3, the signals on the three lines 20-1 to 20-3 of the serial bus 20 are received by the three receiver elements 31-1 to 31-3 as in the related art. . The received signal is input to the serial bus input control unit 33 via three serial bus input lines 32. Thus, the internal circuit 34 performs a predetermined process. (B) Output Operation to Serial Bus 20 FIG. 4 is a time chart for explaining the operation of the self-stack detection circuit 40 of FIG. Each functional unit 30-1
In the self-stack detection circuit 40 in 30-3, while the three serial bus output lines 36 are off, the OR element 4
Since the output terminal of 1 is off, it is inverted by the inverter element 43, the reset terminal R of the counter 44 is turned on, and the count value of the counter 44 is 0.

Next, (B) (i) an output operation in a normal state;
(B) (ii) Output operation at the time of failure will be described. (B) (i) Output operation in normal state When any one of the three serial bus output lines 36 is turned on at the normal operation start timing, the output terminal of the OR element 41 in the self-stack detection circuit 40 is turned on. ,
This is inverted by the inverter element 43 to release the reset of the counter 44, and the enable terminal E of the counter 44 is turned on via the AND element 42, so that the counter 44 starts counting up. When any one of the three serial bus output lines 36 is turned on, the three open collector driver elements 37-1 to 37-1 connected thereto are turned on.
A signal is output on the serial bus 20 via any one of 37-3. As described above, the use of the serial bus 20 is terminated in the normal operation, and the serial bus output control unit 35 is used.
When the serial bus output signal line 36 in the ON state is turned off, the OR element 41 in the self-stack detection circuit 40 is turned off.
Then, the enable terminal E of the counter 44 is turned off via the AND element 42 and the reset terminal R is turned on. Thus, the counter 44 stops counting up and sets the count value to the initial value 0.

(B) (ii) Output operation at the time of failure In the operation at the time of failure, the operation at the start timing is the same as the operation at the time of normal operation. At the time of a failure, the counter 44 keeps counting up because one of the serial bus output lines 36 is not released while being turned on due to the failure of the serial bus output control unit 35. Then, a preset counter overflow value (this value is set to a length that cannot occur in normal operation, and for example, 5 in FIG. 4)
(Set to 0), the counter 44 outputs a carry signal from the carry terminal C. When the carry signal is output, it is inverted by the inverter element 45, and the output enable line 50 is turned off. This allows
It is possible to suppress the data actually output to the serial bus output line 36 from being output to the serial bus 20. The signal of the output enable line 50 is input to the enable terminal E of the counter 44 via the AND element 42 in the self-stack detection circuit 40, and the enable terminal E is turned off. Then, the count-up operation is stopped, and the carry signal is continuously output from the carry terminal C. Thereafter, the output enable line 50 remains off until the serial bus output line 36 turns off and the reset terminal R of the counter 44 turns on.

As described above, this embodiment has the following advantages (a) and (b). It is provided with the self-stack detection circuit 40 in the (a) Each functional unit 30-1 to 30-3, each functional unit 30
-1 to 30-3, a plurality of serial bus output lines
36-3 to 36-3, the duration of each output signal is
And each output signal is
Is also possible. Therefore, for example, the functional unit 3
Even if the serial bus output control unit 35 or the like in 0-1 fails, the serial bus 20 is not adversely affected, and communication between the other functional units 30-2 and 30-3 becomes possible. (B) When each of the functional units 30-1 to 30-3 is accessed by software of a processor connected to the serial bus 20, a certain functional unit (for example, 30-1) is accessed.
By making it impossible to access only the faulty function unit 30-1, it becomes easy to specify the faulty function unit 30-1. 2. Description of the Related Art In a general bus connection device, it is common that data is transmitted and received by connecting functional units via a bus called a system bus including a data bus, an address bus, and a control bus. Since the system bus needs to transmit data at a high speed, the data lines have a width of 32 bits or 64 bits, and the number of signal lines is several tens to one hundred and several tens or more. In the present embodiment, the serial bus 20 is used because if the self-stack detection circuit 40 is provided in such a system bus having a large number of signal lines, the circuit scale of the self-stack detection circuit itself becomes too large. Effective effects cannot be expected when a failure occurs. Therefore,
In the present embodiment, when the serial bus 20 is used,
Since the self-stack detection circuit 40 is provided in each of the functional units 30-1 to 30-3, effective effects as described in the above (a) and (b) can be expected.

Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications (1) and (2). (1) Number of serial buses 20 and functional units 30-
The number of 1 to 30-3 is not limited to the illustrated one, and any number is applicable. (2) The self-stack detection circuit 40 uses the serial bus 2
It is sufficient to have a function of detecting a broken internal state while outputting a transmission signal to 0, and masking the output of the transmission signal when detecting this internal state. It is possible.

As described above in detail, according to the present invention, at each bus connection point of each functional unit connected to the serial bus, a broken state is detected while outputting a signal, and the output of the unit is masked. since spread range of disorders by it is provided a self-stack detection means for preventing the effects of other functional units, a plurality of output lines
The duration of each output signal is measured and each output signal is
It is possible to cope with the case of stacking. Even if a failure occurs in a certain functional unit, communication between other functional units becomes possible without affecting the serial bus. In addition, when each functional unit is accessed by software of a processor connected to the serial bus, only a certain functional unit cannot be accessed, thereby facilitating the specification of a faulty functional unit.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a serial bus connection device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional serial bus connection device.

FIG. 3 is a circuit diagram showing a configuration example of a self-stack detection circuit in FIG. 1;

FIG. 4 is a time chart illustrating the operation of the circuit of FIG. 3;

[Explanation of symbols]

Reference Signs List 20 serial bus 30-1 to 30-3 functional unit 31-1 to 31-3 receiver element 32 serial bus input line 33 serial bus input control unit 34 internal circuit 35 serial bus output control unit 36 serial bus output line 37-1 37-3 Open Collector Driver Element 40 Self-Stack Detection Circuit 44 Counter

──────────────────────────────────────────────────続 き Continued on the front page (72) Michihiro Aoki Inventor, Nippon Telegraph and Telephone Corporation 3-9-1-2, Nishishinjuku, Shinjuku-ku, Tokyo (72) Inventor Seiji Deya 3-19, Nishishinjuku, Shinjuku-ku, Tokyo 2. Nippon Telegraph and Telephone Corporation (72) Inventor Tokuo Hosaka 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) References JP-A-51-29013 (JP, A JP, A 64-12643 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/28-12/46 H04L 29/14

Claims (1)

(57) [Claims] 1. A serial bus comprising a plurality of signal lines.
And connected to the serial bus, via the serial bus
A plurality of functional units that mutually transmit and receive signals,
In the serial bus connection device provided, each of the functional units includes a transmission signal transmitted from inside through a plurality of output lines.
Driver means for outputting to the serial bus, receiving a transmission signal sent from the serial bus,
Receiver means for inputting to the inside through a plurality of input lines
And a relay of output signals output from each of the plurality of output lines.
The duration is measured by the counting means and the output signal
If the duration is within a certain time, reset the counting means.
When the output signal is longer than a certain time
Is the driver according to the carry signal of the counting means.
And a self-stack detecting means for turning off the means .