JPH0546729B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for controlling transmission errors in data transmission.

(Prior Art) In data transmission in which multiple data signals are time-division multiplexed by assembling frames, various methods have been adopted to prevent errors in data signals that occur during transmission. One example is a method in which the receiving device detects an error in the data signal that occurs during transmission and issues a retransmission request to the transmitting device (for example, "Data Communication" edited by Iwao Yamamoto (July 10, 1971))
(P. 167 of the Sanken Report).

Another method is to monitor the data signals individually for a certain period of time and change them from 0 to 1 or 1 within that period.
A method in which an error occurs when a change from ) P.8-6) is known.

(Problems to be Solved by the Invention) However, the former method requires the transmission procedure to be determined for retransmission between the transmitting side and the receiving side, and has drawbacks such as requiring memory for the transmitted data on the transmitting side. It was hot.

Furthermore, the latter method has the disadvantage that when transmitting a plurality of data signals, a monitoring/correction circuit is required for each data signal, resulting in an increase in circuit scale.

The present invention provides a simple error correction means that does not require retransmission requests or individual monitoring/correction circuits for low-speed data transmission errors.

(Means for Solving the Problems) The present invention provides a delay circuit that delays a received signal by one frame in a receiving device, a frame memory that stores one frame of the output of the delay circuit, and error detection of the received signal on a frame-by-frame basis. The frame memory includes an error detection circuit that outputs a control signal when an error is detected, and an inhibit gate that inhibits writing to the frame memory using the control signal.

(Operation) The received signal is delayed by one frame by the delay circuit and input to the frame memory. If there is no error in the received signal, the one-frame delayed signal is sequentially written into the frame memory and read out as an output signal after a certain timing. When an error is detected in the received signal, the prohibition gate prohibits the write operation of the frame memory by the control signal from the error detection circuit, so that the data of the frame immediately before the write prohibition held in the frame memory is A signal is read out as an output signal in place of the data signal of the erroneous frame.

(Embodiment) FIG. 1 is a block diagram of a receiving side device according to an embodiment of the present invention, in which 11 is a received signal input terminal, 12 is a frame synchronization circuit, 13 is an error detection circuit, 14 is a delay circuit, and 15 is a 16 indicates a frame memory write inhibit gate, and 17 indicates an output terminal.

FIG. 2 shows an example of the frame structure of a multiplexed signal input to the received signal input terminal 11 of FIG.
It consists of a frame synchronization signal for establishing frame synchronization, a data signal for m lines, and an error detection code. Parity check codes, cyclic codes, etc. are known as error detection codes, but there is no need to limit them here.

FIG. 3 is a time chart showing the operation of the receiving side apparatus shown in FIG. 1, and for convenience of explanation, shows an arbitrary line extracted from the data signals of m multiplexed lines. In Figure 3, a
is a transmission signal, b is a reception signal, c is a delay circuit output signal, d is a frame memory write control signal, and e is a frame memory read signal, respectively.

This embodiment will be described below with reference to FIGS. 1, 2, and 3. a second from a transmitting device (not shown)
The multiplexed signal shown in the figure is input to the received signal input terminal 11 of the receiving side device shown in FIG. The input multiplexed signal is frame synchronized by a frame synchronization circuit 12, and then an error detection circuit 13 performs error detection on the data signal, and delays the received data by the time required for error detection, that is, one frame time. The data are sequentially written into the frame memory 15 via the delay circuit 14 in accordance with the write clock. Here, the frame memory 15 receives the data signal 1
This is a circuit that stores frames. The data signal written in the frame memory 15 is read out at an appropriate timing (the time indicated by t in FIG. 3, the value is not particularly limited) by the read clock and sent to the output terminal 17.

Next, a case will be described in which an error occurs in the multiplexed signal for some reason during transmission. The error detection circuit 13 shown in FIG. 1 performs an error detection operation on the data signal using an error detection code attached to the end of the frame of the multiplexed signal shown in FIG. 2, and determines whether there is an error in the frame. This information is sent to the prohibition gate 16. That is, if no error is detected, a control signal for opening the inhibit gate 16 is sent to the inhibit gate 16, thereby sending a write clock to the frame memory 15, and transmitting the received data signal delayed by one frame to the frame memory 1.
5 sequentially. When an error is detected, a control signal to close the prohibition gate 16 is sent to the prohibition gate 1.
6 inhibits the write clock to frame memory 15, thereby inhibiting all data signals for that frame from being written to frame memory 15.

Therefore, an error occurs in the transmitted signal a whose logic level is "1" as shown in Fig. 3 due to some reason during transmission, and it is received as the received signal b in which "1" is mistakenly changed to "0" in frames A and B. The case will be explained below. The received signal b is delayed by one frame by the delay circuit 14 shown in FIG.
Sent to 5. On the other hand, the error detection circuit 1 shown in FIG.
3 detects the error occurring in the frames A and B, and sends a frame memory write control signal d of logic level "1" to the inhibit gate 16 shown in FIG. The prohibition gate 16 is the frame memory 16.
By inhibiting the write clock for the two frames A and B, writing of all data signals of the two frames A and B of the delay circuit output signal c to the frame memory 16 is inhibited. During this write prohibition, the data signal of the frame immediately before the prohibition, that is, the data signal of the frame marked with "*" of the delay circuit output signal c shown in FIG. 3, is held in the frame memory 15, and then the write prohibition is disabled. The data signal of this held frame is repeatedly read out until the data signal of the held frame is released and the data signal of a new frame is written. The two frames indicated by the dotted line of the frame memory read signal e read from the frame memory 15 indicate that the data signal of the frame marked with "*" of the delay circuit output signal c is repeatedly read out twice. be.

As explained above, according to this embodiment, if the data signal is a low-speed data signal having a sufficiently long change period with respect to the frame period, the data signal of the frame in which the error occurred is Errors can be easily corrected by replacing the data signal with the data signal of the frame in which no errors have occurred in the past, which is closest to the time.

As an error detection method, in addition to the method of performing error detection calculations directly on the data signal as in the case of parity check codes and cyclic codes, there is also a method of monitoring the regularity of the transmission code as in the case of bipolar code error detection. It is obvious that the same effect can be obtained by using this method.

(Effects of the Invention) As explained above, in the case of transmitting a data signal whose change period is sufficiently long with respect to the frame period, the present invention allows the data signal of the frame in which an error has occurred to be transmitted to the nearest past from the time when the error occurred. Errors can be easily corrected by replacing them with data signals of frames in which no errors have occurred.

SS/SR signals and alarm signals in PCM terminal equipment that change over a long period with respect to the frame period 2
This is useful when transmitting value status information.

In general, transmission equipment is often provided with a function to detect transmission path errors in order to monitor the characteristics of the transmission path. By using it for both road monitoring and error correction control, an economical and efficient device configuration is possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a receiving device according to an embodiment of the present invention, FIG. 2 is a frame configuration diagram of a multiplexed signal to be transmitted, and FIG. 3 is a time chart showing the operation of the receiving device shown in FIG. 1. . 11... Received signal input terminal, 12... Frame synchronization circuit, 13... Error detection circuit, 14... Delay circuit, 1
5...Frame memory, 16...Prohibition gate, 17...
Output terminal.

Claims (1)

[Scope of Claims] 1. A data transmission system in which low-speed data is transmitted in frames, comprising: a delay circuit that causes a receiving device to delay a received signal by one frame; a frame memory that stores one frame of the output of the delay circuit; An error detection circuit that detects transmission errors in units, and when an error is detected by the error detection circuit,
write inhibiting means for prohibiting writing of the received signal to the frame memory, and when no error is detected in the received signal, writes the output of the delay circuit to the frame memory;
The error-free received signal written in the frame memory is read out as an output signal, and if an error is detected, the error-detected received signal is read out as an output signal based on the control signal of the error detection circuit. Writing to the frame memory is prohibited by the write inhibiting means, and one frame of error-free data signal held in the frame memory is written once or for the number of frames of the received signal in which the error is detected. By repeating the data signal a corresponding number of times and reading it out as an output signal, the data signal of one frame with an error is replaced with the data signal of one frame without an error in the past that is closest to the frame with the error. Error control method. 2. The error control system according to claim 1, which detects transmission errors by inserting an error detection code into a frame. 3. The error control method according to claim 1, which monitors a fixed transmission code rule on a frame-by-frame basis and detects transmission errors based on disturbances in the transmission code rule.