JPS5894253A - Detecting system for code error - Google Patents

Abstract

PURPOSE:To reduce both the circuit scale and the power consumption and to decrease the time of detection, by obtaining an exclusive OR between the M-th bit of the information bit and the M'-th bit into which the complementary code is inserted to detect a code error. CONSTITUTION:The input data are fed to a 1-bit shift register 1 by one block, and the M-th and M'-th pulses are extracted. A synchronism deciding circuit 2 decides that the synchronism is obtained when the above-mentioned pulses meet the prescribed frequencies. Even though these pulses do not meet the specification only once, still the contents of the register 1 are shifted by one bit to search after the prescribed pulse and to obtain synchronism. Then an error detecting circuit 4 detects a code error if there is an error pulse since the exclusive OR and the output of an inverting circuit 3 are set at 1. In this system, both the circuit scale and the power consumption are reduced, because a code error detecting circuit and the greater part of a block synchronizing circuit are shared. Furthermore the code error can be detected early since the detection is carried out by one block.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a digital communication system in which N information bits are made into one block, and the information bits of the pattern block are
The present invention relates to a code format in which a complementary code of the Mth bit is inserted into the M'th bit, and relates to a simple code W4 detection method.

Conventionally, the quality of digital communication lines has been maintained by monitoring code errors on the transmission path. Generally, code errors are monitored by receiving devices at terminal repeaters located at both ends of the transmission path. However, if the intermediate relay device installed at the station in the middle of the transmission line can be monitored online, the reliability of the communication line will be improved and the point of failure will be known to be in the direction before the intermediate relay device installed at the station. The narrow detection range makes maintenance easier.

However, when using the conventional parity detection method, it is necessary to read one frame consisting of several blocks and judge whether the number of 1's is odd or even, which increases the circuit size and consumes a lot of power. The disadvantage is that it takes time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a simple code error detection method that has a small circuit scale, low power consumption, and a quick detection time in order to eliminate the above-mentioned drawbacks.

In order to achieve the above object, the present invention uses KPCM communication method 2 to form one block of N information bits, and inserts the complementary code of the M-th bit of the information bits of the scissor block into the y'th column. In the code format, after synchronizing on the receiving side, a code error is detected by taking the exclusive OR of the #M1th bit and the M'th bit. provide. Note that code errors generally occur randomly, so 2 out of 1 block N bits
Code errors can be detected with a high probability even by looking at bits as 1.

An embodiment of the present invention will be described below with reference to the drawings.

The first WJ shows the frame structure, (A) shows the structure of l frame, and @) shows the structure of l block. CAIFiM shows the time chart of the waveforms of each part in Figure 2.
(B) indicates the case where the M'th bit is an error, (CI indicates the error detection pulse, (A), (B), and (C) indicate a, b in Fig. 2). , corresponds to point e.

In the figure, IFi 1-bit shift register, 2 is the 11th period judgment (
b) path, 3 is exclusive OR and inversion rotation, 4 is error detection string 7 round path, F is frame bit, M#'iMt-th bit area, M' is M'-th bit area, NF'iN Indicates the th bit area.

The code configuration used in the present invention is used to suppress consecutive 0's and 1's in a pulse train. This is a code format in which a complementary code is inserted in advance into the M'th bit area. That is, if the Mth bit sign is 1, then M
'th bit sign is 0. If the Mth bit code is 0, the M'th bit code is l. jl Recently used M.

A method for synchronizing at the M'-th code will be explained.

In the case of synchronization, as shown in Fig. 2, the input data is input to the 1-bit shift register 1 one block at a time, the M@th and M'th pulses are taken out, and if, for example, all four pulses are as specified, the synchronization judgment circuit 2 determines that one period has been completed, and if the specified pulse is not passed even once, the contents of the 1-bit shift register I are shifted bit by bit to search for a specified pulse and synchronize. After that, error detection judgment circuit 4ij
, in Figure 3). If there is an I signal, the output of the exclusive OR and inversion circuit 3 will be 1 (like Q), or if the Mth bit sign is 0, the M'th bit sign should be l if it is normal. If is 0 for some reason, the output of the exclusive OR and inversion circuit 3 will be 1 as well.
Therefore, a code error is detected from this K. The synchronization is determined to be out of synchronization, for example, if the pulses of MM' in all five blocks are not as specified. According to this method, most of the code 1IiID detection circuit can be shared with the block synchronization circuit, so the circuit scale is small and the power consumption is also reduced. Further, since code errors are detected every l block, early detection is possible. The method for synchronizing is the frame four rule method. After synchronization, the Mth bit code and M'
It is also possible to use a delay circuit or the like to set the th bit code in a one-time, one-time relationship, and use an exclusive OR circuit to detect a code error from its output.

As explained in detail above, according to the present invention, the circuit scale is small, the power consumption is low, and a change in signal width can be detected early, and the intermediate repeater @Vc installed at the station can be easily installed, thereby preventing damage to the digital communication line. This has the effect of improving reliability and maintenance efficiency.

[Brief explanation of drawings]

Fig. 1 is a frame configuration diagram, Fig. 2 is a block diagram of a code WA detection circuit according to an embodiment of the present invention, and Fig. 3 is a time chart of waveforms of various parts in the case of Fig. 2. is a 1-bit shift register, 2Vi is a synchronization judgment circuit, 3 is an exclusive OR and inversion circuit, 4 is an error detection judgment circuit, F is a frame bit, Mtl! Mth bit area, M'FiM'th bit area, N indicates Nth bit area #.

Claims (1)

[Claims] In a digital communication system, in a code format in which N information bits are set as one block and a complementary code of the M-th bit of the information bits of the block is inserted at the M'-th position,
After synchronizing with reception @, #Mi1st bit and #M'
A code error detection method in which code errors are detected by K by taking the exclusive OR of the bits of honor.