JPH0328860B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention uses a digital communication system in which N pieces of information bits are made into one block, and the complementary code of the M-th bit of the information bits of the block is
This paper relates to a code error detection method when using the M'th inserted code format.

<Background> The quality of digital communication lines has traditionally been maintained by monitoring code errors in the transmission path. Generally, code errors are monitored by receiving devices at terminal repeaters at both ends of the transmission path. However, if an intermediate relay device installed at a station in the middle of the transmission path can be monitored online, it will be possible to determine whether the point of failure is in the direction before the intermediate relay device, and the search range for the failure point will be narrowed, making maintenance easier. becomes.

However, when monitoring code errors using the conventional parity detection method, it is necessary to read one frame consisting of several to several hundred blocks and judge whether the number of "1"s is odd or even. The drawbacks are that synchronization is required, the circuit scale becomes large, and power consumption also increases.

Therefore, in digital communication systems, block synchronization is performed on the receiving side using a code format in which N information bits are treated as one block, and the complementary code of the M-th information bit of the block is inserted at the M'-th position. A method has been proposed in which code errors are detected by calculating the exclusive OR of the M-th bit and the M'-th bit. Incidentally, since code errors generally occur randomly, the state of the transmission path can be monitored with sufficient accuracy by monitoring 2 bits in 1 block of N bits.

However, in order to obtain block synchronization, a method equivalent to frame synchronization is normally used, and requires a bit-synchronized clock signal and circuits such as a synchronization determination circuit and a synchronization protection circuit.

<Summary of the Invention> An object of the present invention is to provide a simple code error detection method that is smaller in circuit scale and consumes less power than a normal code error detection method using block synchronization.

In order to achieve the above-mentioned object, the present invention uses a digital communication method to convert N information bits into one.
In a code format in which the complementary code of the Mth information bit of this block is inserted into the M'th block, the original received pulse train is converted to
A pulse train delayed by the time difference between the Mth bit and the M′th bit, which are known in advance;
A clock signal with a frequency of 1/N of the transmission line frequency is extracted from the pulse train generated by exclusive ORing with the original received pulse train using a bandpass filter, and if there is no transmission line code error, the above One pattern that occurs every N bits in the pulse train generated by exclusive ORing is read out using a clock signal obtained by delaying the above extraction clock signal by a known time in advance, and the Mth bit or M'th bit of the block is read out. It is detected that the above-mentioned 1 pattern becomes 0 pattern due to a transmission line code error in bits.

<Example> An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows the frame structure of the code sequence used in this invention, where A is the structure of one frame, and B is the structure of one frame.
The structure of the block is shown. FIG. 2 is a block diagram of a code error detection circuit according to an embodiment of the present invention, and FIG. 3 is a time chart of waveforms at various parts in FIG.
B, C, D, and E are respectively a, b, and
This corresponds to points c, d, and e.

In the figure, 1 and 4 are delay circuits, 2 is a wave generator, and 3
is the limiter amplifier, F is the frame bit, and M is the M
M′ is the M′th bit area,
N indicates the Nth bit area.

The code structure used in the present invention suppresses the number of consecutive "0"s and the number of consecutive "1"s on the transmission path, and makes the transmission path BSI. That is, if the Mth bit code is "1", the M'th bit code is "0", and the Mth bit code is "0".
If so, the M'th bit code is set to "1".

Therefore, if there is no transmission line code error, the received pulse train input to the input terminal 11 (FIG. 3) is processed using the delay circuit 1 so that the M-th bit code and the M'-th bit code have the same time relationship. When the exclusive OR is performed at 12, one pattern is repeated at a period equal to one block length, as shown by the solid line in FIG. 3C. By passing this signal through a wave generator 2 whose passband is 1/N of the transmission line frequency, a clock signal shown in FIG. Using this extracted clock, the D-type flip-flop 13 detects the above-mentioned one pattern, and the number of code errors output from the terminal 14 is counted.

That is, if the Mth bit code is "1", the M'th bit code is normally "0", and the output of the exclusive OR circuit 12 should be "1", but if something is If the Mth bit code or the M'th bit code is erroneously transmitted for some reason, the output of the exclusive OR circuit 12 becomes "0" as shown by the dotted line in FIG. 3C.

<Effects> As explained in detail above, in this invention, by extracting the frequency component of 1/N of the transmission line frequency dependent on the received pulse train, the synchronization judgment circuit and synchronization necessary for normal block synchronization can be improved. It is possible to realize a code error detection circuit that does not require a protection circuit, has a small circuit scale, has low power consumption, and can be easily installed in an intermediate relay device installed at a station, which has the effect of improving the reliability and maintenance efficiency of digital communication lines. There is.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a frame structure, FIG. 2 is a block diagram showing a code error detection circuit according to an embodiment of the present invention, and FIG. 3 is a time chart showing waveform examples of various parts in FIG. 1...Delay circuit, 2...Wave generator, 3...Amplification circuit, 4
...Delay circuit.

Claims (1)

[Claims] 1 In digital communication systems, multiple blocks each consisting of N information bits are
A code format is used in which a frame is constructed and the complementary code of the M-th bit of the information bits of each block of the frame is inserted into the M'th bit. A band wave whose passband is 1/N of the repetition frequency of the transmission line signal is generated from the pulse train generated by taking the exclusive OR of the pulse train delayed by the time difference with the bit of the transmission path signal and the original received pulse. A clock signal with a frequency that is 1/N of the repetition frequency of the transmission line signal is extracted using a device, and the phase of the extracted clock is used as the synchronization timing to detect a code error from the pulse train obtained by the exclusive OR. Code error detection method.