JPS6163125A - Error control system - Google Patents

Abstract

PURPOSE:To attain ease of error correction by replacing a frame data signal having an error into a frame data signal having no error at the closest time from the occurrence point of time of error. CONSTITUTION:A multiplex signal inputted to a reception signal terminal 11 is subjected to frame synchronization at a frame synchronization circuit 12, an error to a data signal is detected by an error detection circuit 13 and written on a frame memory 15 sequentially via a delay circuit 14 retarding the reception data by one frame time required for error detection according to the write clock. The written data signal is read at a proper timing by a read clock and transmitted to an output terminal 17. On the other hand, when an error is detected in the reception signal, since an inhibition gate 16 inhibits the write of the memory 15 by using the control signal from the circuit 13, a frame data signal just before write inhibition stored in the memory 15 is read as an output signal in place of the erroneous frame data signal.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for controlling transmission errors in data transmission.

(Prior Art) In data transmission in which multiple data signals are time-division multiplexed by assembling frames, various methods have been used to prevent errors in data signals that occur during transmission. One typical example is a method in which a receiving device detects an error in a data signal that occurs during transmission and issues a retransmission request to the transmitting device (for example, see Data Communication J (1971, edited by Iwao Yamamoto).
-7-10) There is a production report P, 167).

Another method is to monitor the data signals individually for a certain period of time, and if the data signal changes from 0 to 1 or from 1 to O twice or more within that period, an error is determined to have occurred and the value of the state before the change is determined. (for example, Proceedings of the 1981 National Conference of the Institute of Electronics and Communication Engineers (8) (1981-3) P
, 8-6) are known.

(Problems to be Solved by the Invention) However, the former method requires a transmission procedure agreement between the transmitting side and the receiving side to avoid retransmission, and also has drawbacks such as requiring a memory for the transmitted data on the transmitting side. there were.

Furthermore, the latter method has the disadvantage that when transmitting a plurality of data signals, a monitoring/correction circuit is required for each data signal, resulting in an increase in circuit scale.

The present invention provides a simple error correction means that does not require retransmission requests or individual monitoring/correction circuits for low-speed data transmission errors.

(Means for Solving the Problems) The present invention provides a delay circuit for delaying a received signal by one frame in a receiving device, a frame memory for storing one frame of the output of the delay circuit, and an error in the received signal for each frame. The error detection circuit includes an error detection circuit that performs detection and outputs a control signal when an error is detected, and a prohibition f-) that prohibits writing to the frame memory using the control signal.

(Operation) The received signal is delayed by one frame by the delay circuit and input to the frame memory. If there is no error in the received signal, the one-frame delayed signal is sequentially written into the frame memory and read out as an output signal after a certain timing. If an error is detected in the received signal, the prohibition P-) prohibits the write operation of the frame memory by the control signal from the error detection circuit, so that the frame immediately before the write prohibition held in the frame memory is The data signal is read out as an output signal in place of the data signal of the erroneous frame.

(Embodiment) FIG. 1 is a block diagram of a receiving side device according to an embodiment of the present invention, in which 11 is a received signal input terminal, 12 is a frame synchronization circuit, 13 is an error detection circuit, 14 is a delay circuit, and 15 is a frame memory, 16 is a frame memory write-inhibited y-tot;
17 indicates output terminals, respectively.

FIG. 2 is an example of the frame structure of a multiplexed signal input to the received signal input terminal 1 in FIG. Become.

As the error detection code, (Litychenok code, cyclic code, etc.) are known, but there is no need to limit them here.

FIG. 3 is a time chart showing the operation of the receiving device shown in FIG. 1. For convenience of explanation, one arbitrary line is extracted from the data signals of m multiplexed lines and shown. be. In FIG. 3, a indicates a transmission signal, b a reception signal, C a delay circuit output signal, d a frame memory write control signal, and e a frame memory read signal.

This embodiment will be described below with reference to FIGS. 1, 2, and 3. The multiplexed signal shown in FIG. 2 from a transmitting device (not shown) is input to the received signal input terminal 11 of the receiving device shown in FIG. The input multiplexed signal is frame synchronized by a frame synchronization circuit 12, and then an error detection circuit 13 performs error detection on the data signal, and delays the received data by the time required for error detection, that is, one frame time. The data is sequentially written into the frame memory 15 via the delay circuit 14 in accordance with the write clock. Here, the frame memory 15 is a circuit that stores data signals for one frame. The data signal written in the frame memory 15 is read out at an appropriate timing (the time indicated by t in FIG. 3, the value is not particularly limited) by the read clock and sent to the output terminal 17.

Next, a case will be described in which an error occurs in the multiplexed signal due to a cause such as on the transmission side. The error detection circuit 13 shown in FIG. 1 performs an error detection operation on the data signal using an error detection code attached to the end of the frame of the multiplexed signal shown in FIG. 2, and determines whether there is an error in the frame. This information is sent to the prohibition gate 16. That is, if no error is detected, a control signal for releasing the prohibited port 16 is sent to the prohibited port 16, thereby sending a write clock signal to the frame memory 15, and transmitting the received data signal delayed by one frame to the frame memory 15. Write in sequence. If an error is detected, the write clock to the frame memory I5 is inhibited by sending a control signal to the inhibit gate 16 to close the inhibit gate 16, and all data signals of the frame are written to the frame memory 15. prohibited.

Therefore, the transmission signal a whose logic level is "1" shown in FIG.
A case where an error occurs for some reason during transmission and frames A and B are received as erroneous reception signals with "1n set to °'0" will be described below. The received signal S is delayed by one frame by the delay circuit 14 shown in FIG. 1 and becomes the delay circuit output signal C, which is sent to the frame memory 15 shown in FIG. On the other hand, the error detection circuit 13 shown in FIG. 1 detects the error occurring in the frames A and B, and sends a frame memory write control signal d of logic level "1" to the inhibit gate 16 shown in FIG. The prohibition gate 16 inhibits the write clock to the frame memory 16 during the two frames A and B, so that all data signals of the two frames A and B out of the delay circuit output signal C are transferred to the frame memory 16. During this write prohibition, the data signal of the frame immediately before the prohibition, that is, the data signal of the frame marked with *'' of the delay circuit output signal C shown in FIG. 3 is held in the frame memory 15. After that, the data signal of the held frame is repeatedly read out until the write prohibition is canceled and the data signal of a new frame is written. The two frames indicated by the dotted line of the frame memory read signal e read out from the frame memory 15 indicate that the data signal of the frame marked 6*” of the delay circuit output signal C is repeatedly read out twice. be.

As explained above, according to this embodiment, if the data signal is a low-speed data signal having a sufficiently long change period with respect to the frame period, the data signal of the frame in which the error occurred is Errors can be easily corrected by replacing the data signal with the data signal of the frame in which no errors have occurred in the past, which is closest to the time.

As a method of error detection, in addition to the method of performing error detection calculation directly on the data signal as in the case of /4' IJ check code, cyclic code, etc., there is also a method of performing error detection operation on the data signal directly as in the case of /4' IJ check code, cyclic code, etc. It is obvious that similar effects can be obtained by monitoring methods.

(Effects of the Invention) As explained above, the present invention provides the following advantages when transmitting a data signal whose change period is sufficiently long with respect to the frame period.
Errors can be easily corrected by replacing the data signal of the frame in which the error occurred with the data signal of the frame in which no error occurred, which is the closest to the time when error 9 occurred.

This is effective when transmitting binary state information that changes over a long period with respect to the frame period, such as SS/SR signals and alarm signals in PCM terminal equipment.

Generally, transmission equipment is often provided with a function to detect transmission path errors in order to monitor the characteristics of the transmission path, but by utilizing this error detection function in the error 9 detection circuit part of the present invention, By using it for both transmission path monitoring and error correction control, an economical and efficient device configuration is possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a receiving device according to an embodiment of the present invention, FIG. 2 is a frame configuration diagram of a multiplexed signal to be transmitted, and FIG. 3 is a time chart showing the operation of the receiving device shown in FIG. 1. . 1 No... Received signal input terminal, 12... Frame synchronization circuit, 13... Error detection circuit, 14... Delay circuit,
15... Frame memory, 16... Prohibited start, 1
7...Output terminal. Figure 1 Figure 3 5Q, 3.27 Showa Year Month Day

Claims (3)

[Claims] (1) In a data transmission system that transmits low-speed data in frames, there is a delay circuit that causes the receiving device to delay the received signal by one frame, a frame memory that stores the output of the delay circuit for one frame, and transmission errors in frame units. an error detection circuit for detecting an error, and means for inhibiting writing to the frame memory when an error is detected by the error detection circuit, and when no error is detected in the received signal, the output of the delay circuit is It is written to the frame memory and read out as an output signal after a certain timing, and if an error is detected, writing to the frame memory is prohibited and the data signal of the frame immediately before the write prohibition held in the frame memory is kept constant. An error control method characterized in that a data signal of a frame with an error is replaced with a data signal of a past error-free frame closest to the frame by reading it as an output signal after a timing. (2) The error control method according to claim (1), which detects transmission errors by inserting an error detection code into a frame. (3) The error control method according to claim (1), which monitors a fixed transmission code rule on a frame-by-frame basis and detects transmission errors due to disturbances in the transmission code rule.