JPH0349443A - Loop synchronizing circuit - Google Patents

Abstract

PURPOSE:To prevent an apparently normal data from being outputted to a transmission signal by fixing the transmission signal to '0' or '1' when a fault takes place to the period of a reception signal frame timing pulse, and resetting a data in a memory when a reception clock is interrupted. CONSTITUTION:The title circuit is a circuit correcting a loop transmission delay time in a loop system data transmission system, and is provided with a means 6 inputting a reception signal frame timing pulse RDF and an overflow pulse of a write address counter 2 to an exclusive OR circuit 4, inputting its output to a D input of a D flip-flop circuit 5 and uses it output to fix a read data from the memory 1 to '0' or '1' and with a means inputting a reception clock RCK to a monostable multivibrator circuit 9, and using its output to reset a data in the memory 1. Thus, the output of an apparently normal data as the transmission signal is prevented regardless of the occurrence of a fault in the reception signal.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a loop synchronization system that corrects loop transmission delay time in a loop data transmission system that transmits information between arbitrary data transmission devices connected in a loop. It is related to circuits.

[Conventional technology]

Conventionally, this type of loop synchronization circuit consists of a memory, a write address counter, and a read address counter, and the read address counter is reset by a transmit signal frame timing pulse, and the write address counter is reset by a receive signal frame timing pulse. It was configured to be reset.

[Problem to be solved by the invention]

However, the conventional loop synchronization circuit described above resets the write address counter using the received signal frame timing pulse, so if an abnormality occurs in the received signal and the received signal frame timing pulse is abnormally regenerated, , the write address counter is frequently reset, and only the area near address uO of the memory is rewritten, and most of the rest remains written with past data.

Furthermore, if the reception clock is interrupted, the write address counter is not counted up, and only a certain location in the memory is rewritten, and most of the remaining data remains written with past data.

Therefore, there is a problem in that even though there is an abnormality in the received signal, apparently normal data may be output as the transmitted signal.

An object of the present invention is to provide a loop synchronization circuit that solves the above problems.

[Means for Solving the Problems] To achieve the above object, a loop synchronization circuit according to the present invention includes a memory, a write address counter, and a read address counter, and the read address counter is connected to a transmission signal frame timing pulse. In a loop synchronization circuit that corrects the loop transmission delay time by resetting the write address counter with the received signal frame timing pulse, the received signal frame timing pulse and the overflow pulse of the write address counter are is input to the exclusive OR circuit, the output of the exclusive OR circuit is input to the D input of the D type flip-flop circuit, and the read data from the memory is 1 at the output of the D type flip-flop circuit.
10" or "11", and means for inputting the received clock to a monomulti circuit and resetting the data in the memory at the output of the monomulticircuit.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a loop synchronization circuit according to the present invention.

In the figure, 1 is a memory circuit, 2 is a write address counter circuit, 3 is a read address counter circuit, 4 is an exclusive OR circuit, 5 is a D-type flip-flop circuit, and 6
is an AND circuit, 7 and 8 are OR circuits, and 9 is a monomulti circuit.

That is, the difference between this embodiment and the conventional example described above is that the received signal frame timing pulse NRDF/
An exclusive OR circuit 4 which inputs F and the overflow pulse of the write address counter circuit 2, and a D type flip-flop circuit 5 which receives the output of this exclusive OR circuit 4 as a D input are provided to form a D type flip-flop circuit. 5 controls the AND circuit 6 to fix the read signal from the memory circuit 1, that is, the read data at "O". Further, at the same time, the received clock is input to the mono multi-circuit 9, and the memory circuit 1 is reset by the output of the mono multi-circuit 9.

The loop synchronization circuit configured in this way writes the received signal @RD" into the memory circuit l using the count value of the write address counter circuit 2, which is reset by the received signal frame timing pulse @RDF" or its own overflow pulse, as an address. , the contents of the memory circuit 1 whose address is the count value of the read address counter circuit 3 which is reset by the transmission signal frame timing pulse 1'TDF'' or its own overflow pulse are transmitted as the transmission signal''
By setting it to 'TD', the loop transmission delay time is corrected.

At this time, the count capacity of the write address counter circuit 2 and the read address counter circuit 3 is set equal to the number of frame bits of the transmitted/received signal. therefore,
The normal cycle of the received signal frame timing pulse ■RDF' and the generation cycle of the overflow pulse are equal and equivalent.

From the above, the received signal frame timing pulse ``RDF'' and the overflow pulse of the write address counter circuit 2 are exclusive-ORed by the exclusive-OR circuit 4, and the output pulse is sent to the D-type flip-flop circuit 5.
By monitoring this, it is possible to determine whether the period of the received signal frame timing pulse "RDF" is normal or abnormal. Therefore, by ANDing the output signal of the D-type flip-flop circuit 5 and the readout signal from the memory circuit l in the AND circuit 6, if the period of the received signal frame timing pulse "RDF" is abnormal, the transmitted signal "TD"'l can be fixed at 110''. In addition, if the received signal frame timing pulse "RDF" and the receive clock "RCK' are cut off at the same time, the mono multi circuit 9 outputs the receive clock "RCK'.
By monitoring "RCK", it is possible to reset the memory circuit l in case of disconnection.

In the above embodiment, the transmission signal @TD" was fixed at 10#, but it may be fixed at 11".

〔Effect of the invention〕

As explained above, the present invention monitors the cycle of the received signal frame timing pulse and the reception clock interruption, and fixes the transmit signal to 00" or "l" if an abnormality occurs in the cycle of the received signal frame timing pulse. By resetting the data in the memory when the reception clock is interrupted, it is possible to prevent apparently normal data from being output to the transmission signal.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. l...Memory circuit 2...Write address counter circuit 3...Read address counter circuit 4...Exclusive OR circuit 5...D type flip-flop circuit 6...AND
Circuit 7, 8...OR circuit 9...Mono multi circuit

Claims (1)

[Claims] (1) Consisting of a memory, a write address counter, and a read address counter, by resetting the read address counter with a transmission signal frame timing pulse and resetting the write address counter with a reception signal frame timing pulse, In a loop synchronization circuit that corrects loop transmission delay time, the received signal frame timing pulse and the overflow pulse of the write address counter are input to an exclusive OR circuit, and the output of the exclusive OR circuit is connected to a D-type flip-flop circuit. means for inputting the received clock to the D input of the flip-flop circuit and fixing the read data from the memory to "0" or "1" at the output of the D type flip-flop circuit; and means for resetting data in the memory at the output of the monomulti circuit.