JPH04275734A - Data output circuit - Google Patents

Abstract

PURPOSE:To obtain the circuit of high operation reliability by constituting the circuit in such a way that an output part reads the invalid data part of input data twice. CONSTITUTION:When an input-side clock is delayed with respect to an output- side clock, a phase supervisory part 41 outputs a detection signal ALM2. When the invalid data part of input data continues for several bits, a detection signal DS is outputted from a bit continuation detection part 42. An enable signal EN2 is outputted from the detection signal ALM2 and the detection signal DS and it is supplied to an output part 40 from a two-time read instruction part 43. The invalid part of input data is read twice in the output part 40 and a bit phase is synchronized by the two-time reading.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output circuit. Specifically, the present invention relates to a data output circuit that reads out data using the station clock instead of the transmission line clock during reception in a system in which a station receives data sent from a digital transmission line.

[0002] In the above-mentioned system, due to reasons such as temperature fluctuations, the transmission line clock (input side clock)
If there is a fluctuation (phase delay or phase lead) with respect to the station clock (output side clock), this fluctuation is absorbed by phase control, that is, the station clock is prevented from corresponding to the change point of the input data. A bit phase synchronization circuit is used to prevent errors from occurring in data discrimination. Such fluctuation absorption of the transmission line clock with respect to the station clock is achieved by reading the data twice or dropping the data.

On the other hand, SONET (sy
chronous optical network)
In the system, the transmission data sent from the sending side includes valid data such as audio data and first status bit, and invalid data such as second status bit. If you do this in parts, you will not be able to obtain the correct valid data string. Therefore, it is necessary to read the data twice or omit the data in the invalid data portion.

0004

2. Description of the Related Art FIG. 4 is a block diagram of a conventional example, and FIG. 5 is an operation timing chart thereof. FIG. 4 shows a data circuit (reception circuit) provided at the station. Input data Z86, Z87, . . . from the transmission line and an input clock are supplied to a serial/parallel converter 10, and the input clock is counted by a ternary counter (WCTR) 11 and made into a window signal WD2. , and is converted into a timing pulse WOTR by the decoder 12 and supplied to the serial/parallel converter 10, and parallel signals Q1, Q2, Q3 are output from each flip-flop.

On the other hand, the output side clock is a ternary counter (R
CTR) 13 and a phase monitoring circuit 14, and is counted by a ternary counter 13, from which a phase monitoring pulse is output and supplied to a phase monitoring circuit 14 and a decoder 15. The phase monitoring circuit 14 from which the timing pulse RCTR is taken out from the decoder 15 monitors the phase relationship between the output side clock and the input side clock (corresponding to the timing of the window signal WD2), and the input side clock is relative to the output side clock. , if there is a delay, request to read twice (ALM
2) (■), if it is progressing, it becomes a missing request (■). Since the present invention shown in FIG. 2, which will be described later, differs from the conventional example only in the operation of requesting to read twice, this operation will be mainly explained, so the conventional example shown in FIG. Explain.

In FIG. 5, the input side clock is delayed at timing to, and the phase monitoring circuit 14 issues a read request twice (AL
M2) and outputs the enable signal EN, the timing "2" of the timing pulse RCTR from the decoder 15 occurs twice in succession. Note that when the input side clock is delayed, the phases of WCTRQ1 to Q3 will also shift accordingly, but if this is illustrated accurately, the timing relationship will become complicated and unclear, so WCTR, Q1
~Q3 timing remains accurate. This timing pulse RCTR is supplied to selectors 16, 17, and 18. On the other hand, the input data enable signal (input data A1, A
2, only timing of A3 is invalid, other timings are valid) and input side clock and timing pulse WCT
R is supplied to a serial/parallel converter 19, and the input data enable signal is converted into a parallel timing signal by each flip-flop and supplied to selectors 17 and 18. If invalid data is detected in the selector 18 and the input clock is ahead of the output clock (not shown in FIG. 5), the phase monitoring circuit 14 is reset, and the update circuit 23 converts the data into ternary By incrementing the count value of the counter 13 by +2, no omission occurs in the invalid data portion.

On the other hand, the outputs Q1 to Q3 of the serial/parallel converter 10 are supplied to a selector 16, where they are converted into a serial state by a timing pulse RCTR.
Output data Z86, Z87 via flip-flop 20
...is output as... At this time, the valid data A4 is read twice and outputted by the timing pulse (timing "2" occurs twice in succession) at the time of the above-mentioned double reading request. Further, the parallel timing signal output from each flip of the serial/parallel converter 19 is made into a serial state by the timing pulse RCTR in the selector 17, and is outputted via the AND gate 21 and the flip-flop 22, which takes an AND with the enable signal EN. Output as a data enable signal. In this case, the output data enable signal is output to the selector 17 at the AND gate 21.
By ANDing the output of and the enable signal EN, a period corresponding to the output data A1 to A4 is set as an invalid part, and is set as a valid part from the timing of the next data A4. That is, by invalidating one of the valid data A4 read twice (the earlier one in terms of timing), correct valid data A4, A5, etc. are obtained.

[0008] As a result, when the input side clock fluctuates with respect to the output side clock, the input data is
By reading the data twice, the output clock is prevented from coinciding with the change point of the input data, thereby preventing errors in data discrimination.

[0009]

[Problem to be Solved by the Invention] By the way, it is possible to provide a plurality of data output circuits having the configuration shown in FIG. There is. In this case, there is a time difference between the enable signal EN (inverted signal of ALM2) supplied to the AND gate 21 of one circuit and the enable signal EN supplied to the AND gate 21 of the other circuit due to temperature fluctuations, for example. may occur.

The conventional circuit shown in FIG. 4 reads valid data twice and uses the enable signal EN to obtain the output data enable signal. If it is not supplied to the output data enable signal, the invalid part of the output data enable signal will only last for a period corresponding to the three output data A1 to A3, as shown by the broken line, and will be obtained by reading the valid input data A4 twice. Therefore, there was a problem that a correct valid data string could not be obtained and operational reliability decreased.

An object of the present invention is to provide a data output circuit with high operational reliability.

0012

[Means for Solving the Problems] FIG. 1 shows a diagram illustrating the principle of the present invention. In the figure, 40 is an output section, and a valid data section (
Z86, Z87,...A4, A5,..., A16, A17)
and invalid data part (A1, A2, A3, A13, A1
4, A15) is read twice according to the read twice instruction and output. Reference numeral 41 denotes a phase monitoring unit that detects that the input clock does not have a phase shift with respect to the output clock. In addition to this, the present invention includes a bit continuity detection section 42 and a twice-read instruction section 43.

The bit continuity detection unit 42 detects invalid data portions (A1, A2,
A3, A13, A14, A15) are detected for several consecutive bits. The twice reading instruction unit 43 is the phase monitoring unit 41
When the detection signal (ALM2) is output from the bit continuation detection section 42 and the detection signal (DS) is output from the bit continuity detection section 42,
an enable signal for reading the input data twice (
EN2) is supplied to the output section (40).

[0014]

[Operation] When the input side clock lags behind the output side clock, the detection signal (ALM2) is sent from the phase monitoring section 41.
is output. On the other hand, when the invalid data portion of the input data continues for several bits, the bit continuity detection section 42 outputs a detection signal (DS). From the double reading instruction section 43,
An enable signal (EN2) is output from ALM2 and DS and is supplied to output section 40. The output unit 40 reads the invalid data portion (A14) of the input data twice. By reading this twice, bit phase synchronization is achieved.

In the present invention, since the data read twice is invalid data, there is no need for an AND gate or the like to invalidate one of the valid data read twice as in the conventional example. For this reason, for example, when driving multiple data output circuits in parallel, the invalid portion of the output data enable signal decreases due to the timing shift of the enable signal supplied to the AND gate, resulting in inconveniences such as valid data being read twice. It will no longer occur.

[0016]

[Embodiment] Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3
show their operation timing charts. In FIG. 2, the same components as those in FIG. 4 are given the same numbers and their explanations will be omitted. In FIG. 2, a serial/parallel converter 10,
The selector 16, decoder 15, and ternary counter 26 output part 40, the ternary counter 11 and phase monitoring circuit 25 output the phase monitoring part 41, and the flip-flop 27 and 2-bit continuous invalid data detection part 28 produce continuous bits. The detecting section 42 includes a serial/parallel converter 19, a selector 18, and an AND gate 29, and a twice reading instruction section 43 is configured, respectively.

As described above, since the present invention differs from the conventional example only in the operation of the read twice request and the missing request, this operation will be mainly explained.

In FIG. 3, if the input side clock (corresponding to the window signal WD2) lags behind the output side clock at timing t1, the phase monitoring circuit 25
2 depending on the H of the window signal WD2 and the rising timing of the phase monitoring pulse from the ternary counter 26.
A reading request (ALM2) is output. It should be noted that in the present invention, in order to avoid obscuring the timing relationship between WCTR and Q1 to Q3, these timings are shown as normal. On the other hand, the input data enable signal is supplied via the flip-flop 27 to the 2-bit consecutive invalid data detection circuit 28, where the invalid data is detected as 2 bits.
It is detected that the bits are consecutive, and a 2-bit consecutive disable detection signal DS is output. The output of the selector 18, the 2-bit consecutive disable detection signal, and the twice-read request signal (ALM2) are supplied to the AND gate 29 and ANDed. At the rising timing t2, the enable signal EN2 is output.

Enable signal EN2 is provided through gate 30 by phase monitoring circuit 25 to reset it, thereby resetting ALM2. At the same time, the phase monitoring pulse from the ternary counter 26 is outputted as H twice in a row, and the timing pulse RCTR from the decoder 15 has a timing of "0" twice in a row. Timing pulse RCTR is supplied to selectors 16, 17, and 18. Output data is output from the selector 16 in accordance with the timing pulse RCTR, and the invalid data A14 is read twice and outputted by the timing pulse RCTR in which the timing "0" is consecutive twice. That is, invalid data is read twice by using the 2-bit continuous disable detection signal DS.

On the other hand, the output of the serial/parallel converter 19 is supplied to the selector 17, set to a serial state by the timing pulse RCTR from the decoder 15, and outputted as an output data enable signal. in this case,
Since input data A13 to A15 are invalid data,
Output data enable signal is output data A13 to A15
The timing period, that is, the period corresponding to 4 data is considered to be an invalid portion.

As described above, in the present invention, since the data read twice is invalid data, the AND gate 21 (FIG. 4) is used to invalidate one of the valid data read twice as in the conventional example. As a result, when multiple data output circuits are driven in parallel as described above, the invalid portion of the output data enable signal is generated at different timings of the enable signal EN supplied to the AND gate 21 as in the conventional example. Inconveniences such as valid data being read twice due to three data pieces will no longer occur. Therefore, operational reliability can be improved compared to the conventional example.

In FIG. 2, 31, 32, and 23 are circuits used to perform deletion when the input block advances relative to the output block. 31 is a selector that detects an invalid data part, 32 is a missing request (ALM1)
23 is an update circuit for updating the count value of the ternary counter 26 by +2 to obtain a decoder output necessary for performing the deletion.

[0023]

[Effects of the Invention] According to the present invention, since the data read twice is invalid data, there is no need for an AND gate or the like to invalidate one of the valid data read twice as in the conventional example. First, when a plurality of data output circuits are driven in parallel, there is no problem such as valid data being read twice due to a timing shift in the enable signal supplied to the AND gate, and operational reliability can be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a block diagram of one embodiment of the invention.

FIG. 3 is an operation timing chart of the present invention.

FIG. 4 is a block diagram of a conventional example.

FIG. 5 is a conventional operation timing chart.

[Explanation of symbols]

10, 19 Serial/parallel converter 11, 26
Ternary counters 12, 15 Decoders 16, 17, 18 Selector 25 Phase monitoring circuit 27 Flip-flop 28 2-bit continuous invalid data detection circuit 29 AND gate 40 Output section 41 Phase monitoring section 42 Bit continuation detection section 43 Twice reading instruction section

Claims (1)

[Claims] [Claim 1] Valid data portion (Z86, Z87,...
, A4, A5, ..., A16, A17...) and invalid data part (A1, A2, A3, A13, A14, A15)
an output unit (40) that reads the input data twice in response to an instruction and outputs the result, and a phase monitoring unit (41) that detects that the input clock has a phase shift with respect to the output clock. ), the data output circuit outputs data with bit phase synchronization by reading the input data twice when the phase shift occurs, the invalid data portion ( A bit continuity detection unit (42) that detects that several bits (A1, A2, A3, A13, A14, A15) are consecutive.
and a detection signal (ALM2) from the phase monitoring section (41).
is output and the detection signal (DS) is output from the bit continuity detection section (42), the input data is
It consists of a twice reading instruction section (43) that supplies an enable signal (EN2) for reading twice to the output section (40), and the output section (40) reads the invalid data part (A14) of the input data. A data output circuit characterized in that it is configured to be read twice.