JP3246096B2 - Self-diagnosis device for digital equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-diagnosis device for digital equipment for detecting an abnormality in a transmission line (cable, VTR, etc.) for transmitting digital video data, for example.

[0002]

2. Description of the Related Art For example, in a digital VTR, video data is transmitted in the form of serial data when transmitting video data to / from another video device. In order to transmit video data in the form of serial data in this manner, a transmission line having good high-frequency characteristics is required. Therefore, in this type of digital VTR,
It has been proposed to add a self-diagnosis device for judging whether or not the video data was successfully transmitted.

FIG. 3 shows a self-diagnosis device for a digital device proposed by the present applicant. In FIG. 3, 1
Indicates a digital VTR as a whole. The 10-bit parallel video data DVp output from the digital video output circuit 2 is converted into serial video data DVs by a parallel / serial conversion circuit (P / S conversion circuit) 3.
After that, the video signal is supplied to another video device, for example, a digital VTR 20 via the transmission line L1.

The serial video data DVs output from the digital VTR 20 is transmitted via a transmission line L2 to the serial / parallel conversion circuit (S) of the digital VTR 1.
After being converted into 10-bit parallel video data DVp by a / P conversion circuit 4, the video data DVp is supplied to a predetermined signal processing circuit (not shown).

[0005] Reference numeral 5 denotes a self-diagnosis device added to the digital VTR 1. That is, the video data DVp output from the output circuit 2 is
1 and a 1-bit transmission data parity code Pa
Is generated, and the parity code Pa is supplied to the FIFO memory 52 as a dual port memory. The parity code Pa is the video data D output from the output circuit 2.
Memory 52 at the timing of clock CK synchronized with Vp.
Are written sequentially. Here, the write address pointer is sequentially incremented at the timing of the clock CK, and the SAV (Start of A
ctive Video), and is reset by a reference synchronization signal DSA synchronized with the ctive video.

The video data DVp output from the S / P conversion circuit 4 is supplied to a synchronization detection circuit 53,
V is detected, and a reference synchronization signal SDSA synchronized with the detected SAV is supplied from the synchronization detection circuit 53 to the memory 52. The reading of the memory 52 is performed by the clock S synchronized with the video data DVp output from the S / P conversion circuit 4.
This is performed at the timing of CK. Here, the read address pointer is sequentially incremented at the timing of the clock SCK, and is reset by the reference synchronization signal SDSA.

As a result, the P / S of the digital VTR 1 is
The video data DVs output from the conversion circuit 3 is fed back to the S / P conversion circuit 4 via the transmission line L1, the digital VTR 20, and the transmission line L2, for a delay time.
The parity code Pa written in the memory 52 is read out with a delay. The parity code Pa read from the memory 52 is supplied to the comparison circuit 54.

The video data DVp output from the S / P conversion circuit 4 is supplied to a parity generation circuit 55 to generate a 1-bit feedback data parity code SPa.
This parity code SPa is supplied to the comparison circuit 54.
The comparison circuit 54 compares the parity codes Pa and SPa, and when the parity codes Pa and SPa do not match, the count clock is supplied to the counter 56 and incremented. The counter 56 has a synchronization detection circuit 5
3, the reference synchronization signal SF of the field period is supplied as a reset signal. As a result, based on the count result K of the counter 56, a bit error is detected for each field, and an abnormality or the like of the transmission lines L1 and L2 is detected.

Although not described above, a FIFO memory 52 having a number of stages corresponding to the number of samples of one line of video data DVp is used. In the case of components, there are 1716 stages in the 525 system and 1728 stages in the 625 system (CCIR601, SMPTE1
25M).

FIG. 4 shows the relationship among a write word address, a write address pointer, a read word address, and a read address pointer when a FIFO memory 52 of 1728 stages is used in the component 625 system.

In this case, the number of address pointers is 1728
It is. On the write side, the parity code Pa is written to the memory 52 every time the clock CK is input. The write address is indicated by a write address pointer. The write address pointer is set to 0 by the reference synchronization signal DSA.
And every time the clock CK is input,
, 1727, are reset to 0 by the next reference synchronization signal DSA, and the count-up operation to 1, 2,..., 1727 is repeated every time the clock CK is input. Become.

On the read side, the parity code Pa is read from the memory 52 every time the clock SCK is input. The read address is indicated by a read address pointer. The read address pointer is reset to 0 by the reference synchronizing signal SDSA which is delayed from the reference synchronizing signal DSA, and thereafter, every time the clock SCK is input, 1, 2,.
···, is counted up to 1727. Further, the read address pointer is set to 0 by the next reference synchronization signal SDSA.
.., 1727 each time the clock SCK is input, and thereafter the count-up operation is repeated in the same manner.

By the above-described write and read operations of the memory 52, the parity code Pa is delayed by a predetermined time (within one line) corresponding to the delay amount of the digital data DVs by the transmission lines L1 and L2.

[0014]

By the way, the delay amount due to 1728 stages is 1728/27 = 64 μsec because the clock frequency is 27 MHz. Therefore, if the delay amount of the video data DVs due to the transmission lines (coaxial cables) L1 and L2 is within 64 μsec, normal data comparison can be performed.

However, when the transmission lines L1 and L2 are, for example, 400 m in a round trip, the delay amount of the video data DVs by the transmission lines L1 and L2 is about 2 μsec, and it is necessary to obtain a delay amount of 64 μsec as described above. The FIFO memory 52 has no video data DVp.
Having the number of stages corresponding to the number of line samples was uneconomical in terms of power consumption and cost.

Therefore, it is conceivable to reduce the number of stages of the memory 52 to such an extent that a required delay amount can be obtained. However, if the number of stages in the memory 52 is simply reduced, a portion where writing overtakes reading occurs near the reset of the address pointer. As a result, data is lost, a normal data comparison cannot be performed, and an abnormality in the transmission path is accurately detected. There was a problem that it became impossible.

FIG. 5 shows a write word address, a write address pointer, and a write word address when an 82-stage FIFO memory 52 is used in the component 625 system.
The relationship between the read word address and the read address pointer is shown.

In this case, the number of address pointers is 82. On the write side, the parity code Pa is written to the memory 52 every time the clock CK is input. The write address is indicated by a write address pointer. The write address pointer is reset to 0 by the reference synchronizing signal DSA, and every time the clock CK is input, 1, 2,.
, 81, and the count-up operation of 0, 1, 2, ..., 81 is repeated by the clock CK. After 1,721 words are counted up to 0, 1, 2, 3, 4, 5 each time the clock CK is input, and 0 is counted by the next reference synchronization signal DSA of 1727 words.
And the above-described count-up operation is repeated each time the clock CK is input.

On the read side, the parity code Pa is read from the memory 52 every time the clock SCK is input. The read address is indicated by a read address pointer. The read address pointer is reset to 0 by the reference synchronization signal SDSA which is delayed from the reference synchronization signal DSA. Next, the read address pointer is clock SC
.., 81 each time K is input.
, 81 are repeated. 1
After 721 words, each time the clock SCK is input, it is counted up to 0, 1, 2, 3, 4, 5 and 17
It is reset to 0 by the next reference synchronization signal SDSA of 27 words, and the above-described count-up operation is repeated each time the clock SCK is input.

If the reference synchronizing signal SDSA lags behind the reference synchronizing signal DSA by 6 clocks or more, before the read side reads out the data of 1722 to 1727 words from the addresses 0 to 5, the write side changes the addresses to 0-5. Since 0 to 5 words of data are written, 1722 to 1727 words of data are lost. As a result, normal data comparison cannot be performed.

In view of the above, the present invention provides a self-diagnosis apparatus for digital equipment which can reduce the number of memory stages without causing a problem that normal data comparison cannot be performed.

[0022]

SUMMARY OF THE INVENTION According to the present invention, transmission data having digital data of a predetermined number of samples per fixed period or data related to the transmission data is transmitted via a transmission line via a delay means. In a self-diagnosis device for a digital device that detects an abnormality in a transmission line by comparing the returned feedback data or data related to the returned data, a delay unit is configured by a dual port memory, and a write address of the dual port memory is set. The read address of the dual port memory is reset every fixed period of the feedback data while the transmission data is reset every fixed period, and the substantial address number of the dual port memory is set to an integral number of the predetermined number of samples. Is what you do.

[0023]

According to the present invention, the write address and the read address of the dual port memory are not reset in the middle, and the data can be prevented from being overwritten by the read and the data is lost. Therefore, the number of memory stages can be reduced without causing a problem that normal data comparison cannot be performed.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a self-diagnosis device for digital equipment according to the present invention will be described below with reference to FIG.
This example is a digital VT of the component 625 system.
This is an example applied to R. In FIG. 1, portions corresponding to those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 1, reference numeral 58 denotes a FIFO memory, which corresponds to the FIFO memory 52 in the example of FIG. Although the number of stages of the FIFO memory 52 in the example of FIG. 3 is set to the number of stages corresponding to the number of samples of one line of the video data DVp, in this example, the number of stages of the memory 58 is 24 times the number of samples of one line of the video data DVp. It is 72 steps which is 1/72.

Since the clock frequency is 27 MHz, the amount of delay due to the 72 stages is 72/27 ≒ 2.67 μs.
ec. Therefore, the transmission path (coaxial cable) L
1, L2, the delay amount of the video data DVs is 2.67.
Normal data comparison can be performed within μsec.

The other structure of this embodiment is the same as that of the embodiment shown in FIG.

In the above configuration, the FIFO memory 58
Will be described.

FIG. 2 shows the relationship among a write word address, a write address pointer, a read word address, and a read address pointer.

In this case, the number of address pointers is 72. On the write side, the parity code Pa is written to the memory 58 every time the clock CK is input. The write address is indicated by a write address pointer. The write address pointer is reset to 0 by the reference synchronizing signal DSA, and every time the clock CK is input, 1, 2,.
, 71, and the count-up operation of 0, 1, 2, ..., 71 is repeated by the clock CK.

After this count-up operation is repeated 24 times, it is reset to 0 by the next reference synchronization signal DSA,
Each time the clock CK is input, the above-described count-up operation is repeated again. As described above, the count-up operation of the write address pointers 0, 1, 2,..., 71 is not reset halfway by the reference synchronization signal DSA.

On the other hand, on the read side, the parity code Pa is read from the memory 58 every time the clock SCK is input. The read address is indicated by a read address pointer. The read address pointer is reset to 0 by the reference synchronization signal SDSA which is delayed from the reference synchronization signal DSA. Next, the read address pointer is clock SC
.., 71 each time K is input.
, 71 are repeated.

After this count-up operation is repeated 24 times, the count-up operation is reset to 0 by the next reference synchronization signal SDSA, and the above-described count-up operation is repeated again every time the clock SCK is input. As described above, the count-up operation of the read address pointers 0, 1, 2,..., 71 is not reset halfway by the reference synchronization signal SDSA.

As described above, in this embodiment, the write address pointer and the read address pointer 0, 1,
The reset is not performed in the middle of the count-up operation of 2,..., 71, so that the write overtakes the read and the data is lost as in the case where the number of stages of the FIFO memory is 82 as described above. And normal data comparison can be performed.

In the above embodiment, the FIFO memory 58 has 72 stages.
8 is greater than 0, 1, 2,... As the write address pointer and the read address pointer.
There is no problem if the count-up operation of 71 is repeated.

In the above-described embodiment, the number of stages in the FIFO memory 58 is 72, which is 1/24 of the number of samples in one line. However, an integer of the number of samples in one line depends on a required delay amount. Needless to say, the number of stages can be changed with a restriction of one-half.

In the above embodiment, the present invention is applied to the digital VTR of the component 625 system. However, the present invention can be similarly applied to the digital VTR of the component 525 system. Also in this case, the number of stages of the FIFO memory is set to an integer fraction of the number of samples of one line of the video data DVp. 4: 2: 2 digital video data (CCIR601, SMPTE1
25M) is 1716 words / line for the 525 system and 1728 words / line for the 625 system.

Therefore, when a delay of about 2 μsec is required in the component 525 system, the number of stages of the FIFO memory is 1/22 of the number of samples per line.
It may be a step. Since the clock frequency is 27 MHz, the amount of delay by the 78 stages is 78/27 ≒ 2.89.
μsec. In this case, the write address pointer and the read address pointer are 0, 1, 2,.
If the configuration is such that the count-up operation of... 77 is repeated, there is no problem even if the number of stages of the FIFO memory is 78 or more.

Also, if the number of stages of the FIFO memory is 78 and the number of address pointers can be switched between 72 and 78 in the 625 system and the 525 system, respectively, the system can be efficiently applied to both the 625 system and the 525 system. Become like That is, 6
In the 25 system, the count-up operation of 0, 1, 2, ..., 71 is repeated as a write address pointer and a read address pointer. In the 525 system, 0, 1, 2, ..., as a write address pointer and a read address pointer. , 77 are repeated.

In the above embodiment, the parity code Pa generated from the transmission data is compared with the parity code SPa generated from the feedback data, and the transmission lines L1 and L2 are compared.
In this invention, the transmission data L is directly compared with the transmission data and the feedback data.
1 and L2 can be similarly applied.

In the above-described embodiment, a digital VTR is shown as an example of a digital device. However, the present invention is also applicable to a self-diagnosis device for other digital devices which transmits digital data via a transmission line. Of course, it can be applied to

[0042]

According to the present invention, the write address and the read address of the dual port memory are not reset in the middle, the data does not overtake the reading and the data is not lost, and the normal data comparison can be performed. The number of memory stages can be reduced without causing the problem of being impossible, which is effective in terms of power consumption and cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a self-diagnosis device for digital equipment according to the present invention.

FIG. 2 is a diagram showing a relationship among a write word address, a write address pointer, a read word address, and a read address pointer in the FIFO memory of the example of FIG.

FIG. 3 is a block diagram illustrating a configuration of an example of a self-diagnosis device for a digital device.

FIG. 4 is a diagram showing a relationship among a write word address, a write address pointer, a read word address, and a read address pointer in the FIFO memory of the example of FIG. 3;

FIG. 5 is a diagram showing a relationship among a write word address, a write address pointer, a read word address, and a read address pointer when the number of stages of the FIFO memory is reduced.

[Explanation of symbols]

 1,20 digital VTR 2 digital video output circuit 3 parallel / serial conversion circuit (P / S conversion circuit) 4 serial / parallel conversion circuit (S / P conversion circuit) 5 self-diagnosis device 51,55 parity generation circuit 53 synchronization detection circuit 54 Comparison circuit 56 Counter 58 FIFO memory

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 29/14 H04L 1/00

Claims (2)

(57) [Claims] 1. Feedback data obtained by returning transmission data having digital data of a predetermined number of samples or data related to the transmission data via a delay unit after a predetermined period, or returning the transmission data via a transmission path. In a self-diagnosis device for a digital device for detecting an abnormality in the transmission path by comparing the data with data related to the data, the delay means is constituted by a dual port memory, and the write address of the dual port memory is set to The read address of the dual port memory is reset every fixed period and the read address of the dual port memory is reset every fixed period of the feedback data, and the substantial number of addresses of the dual port memory is set to an integral number of the predetermined number of samples. A self-diagnosis device for digital equipment. 2. The self-diagnosis apparatus for digital equipment according to claim 1, wherein said digital data is digital video data, and said number of addresses is switched in accordance with a system of said digital video data.