JPH09284356A - Data reception controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data reception controller whereby data transfer is continued even when a parity error occurs. SOLUTION: A write pointer 102 and a read pointer 105 control an address for reading and writing data and its timing as against FIFO 101 which stores reception data and detect the parity error of data. The write pointer 102 and the read pointer 105 are provided with a pointer comparator 111 detecting the coincidence of the addresses in input/output data concerning data where the parity error occurs. When the write pointer 102 and the read pointer 105 detect the parity error and also the pointer comparator 111 detects the address coincidence of the write pointer 102 and the read pointer 105, a write pointer correcting circuit 103 or a read pointer correcting circuit 106 resets the write pointer 102 and the read pointer 105.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reception control device, and more particularly to an optical interface data reception control device for receiving data exchanged by connecting large computers.

[0002]

2. Description of the Related Art Conventionally, in a data transmission system using an optical cable, as shown in FIG. 2, a transmission side computer having a data transmission control unit 6 and an optical transmission control unit 4, and an optical reception control unit 3 are provided. The reception side computer is provided with a data transmission control unit 1 and an inter-byte synchronization control unit 2. The receiving computer is connected to the transmitting computer by a plurality of optical cables 5.

The data transmission control unit 6 controls the transmission of the data stored in the main storage device 7. The optical transmission control unit 4 is composed of a plurality of optical transmission individual control units 401 to 40n that perform the above-mentioned data conversion and signal conversion for each unit data, convert the data to be transmitted from parallel data to serial data, and generate an electrical signal. Is converted into an optical signal, and data transfer timing is generated.

The optical reception control section 3 converts the received data from an optical signal into an electrical signal, and further converts serial data into parallel data, and performs the signal conversion and data conversion for each unit data. At the same time, a plurality of optical transmission individual control units 40 that generate data storage timings
It is composed of 1 to 40n. The data transmission control unit 1 stores the received data, and the inter-byte synchronization control unit 2 stores
This is for synchronizing the received data.

The data reception control unit 1 is connected to each of the optical reception individual control units 301 to 30n, and the FIFO 101 to which the transfer data from the optical reception individual control units 301 to 30n is written is written. Is equipped with. The FIFO 101 is connected with a write pointer 102 for designating an address for writing transfer data. The write pointer 102 includes a write pointer update control circuit 1 for controlling the address update of the FIFO 101.
03 is provided.

The write pointer 102 is also connected to a 1st data detection circuit 104 for detecting the start of address update of the write pointer 102 (pointer value indicates 1). The FIFO 101 is connected with a read pointer 105 for instructing the address of the data so as to read the data stored therein. The read pointer 105 is connected to a read pointer update control circuit 106 for controlling the address update of read data.

The write pointer 102 is provided with a parity check circuit (PC) 108 for performing a parity check when updating the address. Further, the write pointer 102 and the read pointer 105 are connected to a pointer comparator 109 that detects a match between the values of these addresses. Further, in the parity check circuit 108 and the pointer comparator 109, when the parity check circuit 108 detects a parity error and when the pointer comparator 109 detects that the address values match,
A fault detection circuit 110 for controlling system down is connected.

The inter-byte synchronization control section 2 comprises a plurality of data reception control sections 1. 1s of each data reception control unit 1
To the t data detection circuit 104, a skew compensation circuit 201 that receives this output and compensates the time until the data of the first data line is written in all the FIFOs 101 and generates the data read timing is connected. A read counter 202 that counts the data written in the FIFO 101 is connected to the skew compensation circuit 201. An inter-byte synchronization register 203 for storing the output data is connected to each FIFO 101.

In the conventional system having the above structure,
The data in the main storage device 7 is converted from parallel data to serial data by the optical transmission individual control units 401 to 40n via the data transmission control unit 6 and from an electrical signal to an optical signal. Data of byte (unit data) is transferred respectively. This data has 64 bytes (1 frame) as shown in Fig. 3.
1-byte data (synchronization pattern) S for synchronization control called a synchronization pattern is inserted in a unit. In FIG. 3, Dxxx means data. Further, the received data is converted from an optical signal into an electric signal in the optical reception individual control units 301 to 30n, and further converted from serial data into parallel data.

Here, the individual optical reception control units 301 to 30n
Detects the synchronization pattern for every 65 bytes to confirm that the individual optical reception control units 301 to 30n are synchronized. Then, for example, when the optical reception individual control unit 301 detects the synchronization pattern, in order to write the data to the FIFO 101 through the signal line 802, the data storage timing that sets High for 64 clocks and Low for the next clock Every time a sync pattern is detected, the write pointer update control circuit 103 and the FIFO 101 are notified of the data storage timing via the signal line 801.

The data storage timing is High.
At h, the write pointer update control circuit 103 starts the address update of the write pointer 102 and repeats the address update every clock. At the same time, FIF
The O 101 writes the data sent via the signal line 802 to the address indicated by the write pointer 102.

When the 1st data detection circuit 104 detects the start of address update of the write pointer 102 (the pointer value indicates "1"), the skew compensation circuit 20
1 compensates the time until the data of the first data line is written in all the FIFOs 101. This allows
The skew difference caused by the difference in the length of each optical cable is absorbed to synchronize the bytes. Skew compensation circuit 20
1 notifies the read counter 202 of the completion of this time compensation.

Upon receiving this notification, the read counter 202 counts 64 words of data written in the FIFO 101, and notifies the skew compensation circuit 201 of the end of the count. The skew compensation circuit 201 generates a read timing that becomes High for 64 clocks from the completion of writing the data of the first data line to all the FIFOs 101 to the notification of the end of the count of the read counter 202, and reads through the signal line 803. Notify the pointer update control circuit 106.

When the data read timing is High, the read pointer update control circuit 106 starts the address update of the read pointer 105 and repeats the address update every clock. Then, the read pointer 105
The data at the address indicated by is read from the FIFO 101, and the read data is input to the inter-byte synchronization register 203 of the inter-byte synchronization control unit 2 and transferred.

When the parity check circuit (PC) 107 of the write pointer 102 detects a parity error when updating the address, the write pointer 102 is
The value of the address is retained without updating. In this state, the FIFO 101 sets the data storage timing to H
Even if it is high, this data is not written. Data is read from the FIFO 101 until the pointer comparator 109 detects a match between the address values of the write pointer 102 and the read pointer 105, together with the data read from the FIFO 101 of another data reception control unit.
It is input to the inter-byte synchronization register 203 of the inter-byte synchronization control unit 2 and transferred.

On the other hand, when the pointer comparator 109 detects the coincidence of these address values, the fault detection circuit 110
Shuts down the entire data reception control device. Similarly, the parity check circuit 1 of the read pointer 105
Even when 08 detects a parity error at the time of updating the address, the failure detection circuit 110 shuts down the entire data reception control device.

[0017]

By the way, the data exchanged between the nodes in the data transmission device tends to have a large capacity, and therefore the number of optical cables used for data transmission tends to increase. Therefore, FI
The number of data reception control units equipped with FOs, write pointers, and read pointers increases, and the failure rate increases accordingly. In the above conventional data reception control device, when a parity error is detected in the parity check circuit provided in each of the write pointer and the read pointer, the FIFO does not function, and this causes the system to go down and data transfer can be performed. There was a problem of disappearing.

An object of the present invention is to provide a data reception control device capable of continuing data transfer when a parity error occurs.

[0019]

A data reception control apparatus of the present invention which solves the above-mentioned problems, is a buffer means for temporarily storing parallel received data for each unit length, and an object to be written in the buffer means. A first means for managing the address of the data, a second means for controlling the timing of writing the data to be written into the buffer means, and a third means for detecting the occurrence of a parity error in the data at the time of writing are provided. Write control means, fourth means for managing addresses of data written in the buffer means, fifth means for controlling read timing from the buffer means, and detection of occurrence of parity error in data at the time of reading. The read control means including the sixth means, the comparing means for determining the coincidence of the addresses at the time of writing and the reading, and the data read from the buffer means are the same. A synchronous control means for performing control, a means for restarting the write control means when the write control means detects a parity error, and the comparing means detects an address match, and the read control means. It has means for restarting the read control means when a parity error is detected and the comparison means detects an address match.

In a preferred form of the data reception control device, the synchronization control means is provided with a correction means for correcting the data in which the parity error is detected by the read control means.

[0021]

DETAILED DESCRIPTION OF THE INVENTION A data receiving apparatus according to an embodiment of the present invention will be described below with reference to FIG. In the data receiving apparatus of FIG. 1, the same components as those of the conventional data receiving apparatus shown in FIG.
A description of such components will be omitted. Similarly, the operation when the parity error failure does not occur is substantially the same as that of the conventional data receiving apparatus described above, and therefore the description thereof is omitted.

In FIG. 1, the data reception control unit 1 of the present embodiment resets the write pointer 102 when a parity error is detected, instead of the failure detection circuit 110 which performs control for bringing down the system due to a parity error failure. And a read pointer correction circuit 111 for resetting the read pointer 105 when a parity error is detected.

That is, the write pointer correction circuit 112.
Is the write pointer 102 and the parity check circuit 10.
7 and the read pointer correction circuit 112 is interposed between the read pointer 105 and the parity check circuit 108, respectively. Further, the write pointer update control circuit 103 includes a parity check circuit 107.
However, a parity check circuit 108 is connected to each of the read pointer update control circuits 106.

Further, the inter-byte synchronization control unit 2 has an EC
A C correction circuit 204 is provided. The ECC correction circuit 204 functions to correct the output data of the inter-byte synchronization register 203.

Next, the operation of this embodiment will be described.
That is, when the parity check circuit 107 of the write pointer 102 detects a parity error when updating the address, the write pointer 102 holds the address value without updating. In this state, the FIFO 101
Does not write data even when the data storage timing is High.

In this case, data is read from the FIFO 101 until the pointer comparator 109 detects that the address values of the write pointer 102 and the read pointer 105 match. This data is input to the inter-byte synchronization register 203 of the inter-byte synchronization control unit 2 together with the data read from the FIFO 101 of the other data reception control unit, and transferred via the ECC correction circuit 204.

When the pointer comparator 109 detects that the address values of the write pointer 102 and the read pointer 105 match, the read pointer update control circuit 1
06 suppresses the address update of the read pointer 105. Then, when the data storage timing becomes Low, the write pointer correction circuit 110 resets the write pointer 102 in which the parity error is detected. As a result, the FIFO 101 returns to the normal operation from the next frame.

On the other hand, when the parity check circuit 108 of the read pointer 105 detects a parity error at the time of updating the address, the address value is held without updating the read pointer 105. Then, in this state, the FIFO 10 is used until the data read timing becomes Low.
Although the data read from 1 is indefinite data, the data is corrected by the ECC correction circuit 204 via the inter-byte synchronization register 203 of the inter-byte synchronization control unit 2 and read from the FIFO 101 of another data reception control unit. Transferred with data.

The data read timing is Lo
When it becomes w, the read pointer correction circuit 111 resets the read pointer 105 in which the parity error is detected. As a result, the FIFO 101 can return to normal operation from the next frame.

As described above, in the data reception control apparatus of this embodiment, even if a data parity error occurs in the write pointer 102 or the read pointer 105, the data receiving operation can be automatically restored. , Data transfer can be continued without system down.

Further, since the output data of the FIFO 101, which has failed due to the parity error failure, is also corrected by the ECC correction circuit 20, the data can be reliably received.

[0032]

As is apparent from the above description, according to the data reception control device of the present invention, the data reception operation is automatically restored even if a parity error occurs, so that the system does not go down. , Data transfer can be continued. Further, the data in which the parity error is detected is automatically corrected by the correction means, so that the data can be reliably received.

[Brief description of drawings]

FIG. 1 is a block diagram of a data reception control device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional data reception control device.

FIG. 3 is an explanatory diagram of data handled by a data reception control device.

[Explanation of symbols]

 1 data reception control unit 2 inter-byte synchronization control unit 3 optical reception control unit 5 optical cable 101 FIFO 102 write pointer 103 write pointer update control circuit 105 read pointer 106 read pointer update control circuit 107 parity check circuit 109 pointer comparator 110 write pointer correction Circuit 111 Read pointer correction circuit 204 ECC correction circuit 301 to 30n Optical reception individual control unit

Claims (2)

[Claims] 1. Buffer means for temporarily storing data received in parallel for each unit length, first means for managing an address of data to be written into the buffer means, and buffer means for the data to be written. Write control means having a second means for controlling the write timing to the memory, and a third means for detecting the occurrence of a parity error in the data at the time of writing, and managing the address of the data written in the buffer means. Read control means including a fourth means for controlling the read timing from the buffer means, a fifth means for controlling the read timing from the buffer means, and a sixth means for detecting the occurrence of a parity error in the data at the time of reading; A comparison means for determining the coincidence of addresses, a synchronization control means for controlling the synchronization between the data read from the buffer means, and a write error control means for the parity error. And a means for restarting the write control means when the comparison means detects an address match, and the read control means detects a parity error, and the comparison means detects an address match. And a means for restarting the read control means. 2. The data reception control device according to claim 1, wherein the synchronization control means includes a correction means for correcting data in which a parity error is detected by the read control means.