KR940007555B1 - Td/bus interface method of network synchronous apparatus - Google Patents

Abstract

The method interfaces a master clock generation processor of a digital processing phase locked loop and a peripheral processor in low class processor board through a telephone device bus. The method includes the steps of: (A) checking that a peripheral processor (PP) is in normal mode when a data is transmitted from a master clock generation processor (MGCP); (B) reading a first byte of a transmission buffer and transmitting data when the first byte of a buffer is H'oo; (C) checking the first byte of a buffer after a certain number of tries when the first byte of a buffer is not H'oo; and (D) recording the abnormal state of a PP and terminating the transmission.

Description

TD bus interface method of network synchronizer

1 is a connection diagram of triplexed MGCP and PP.

2 is a MGCP block diagram.

3 is a PP block diagram.

4 is a detailed view of PPTDI of PP.

5 is a flow chart of data transmission from MGCP to PP.

6 is a flowchart of data reception from MGCP to PP.

Figure 7 Flowchart of data transmission from PP to MGCP.

8 is a flowchart of receiving data from PP to MGCP.

* Explanation of symbols for main parts of the drawings

11: DP-PLL (MGCP0) 12: DP-PLL (MGCP1)

13: DP-PLL (MGCP2) 14: TD Bus

15: PP

The present invention relates to a TD between a control processor MGCP (Master clock Generation Processor) and a subprocessor PP (Peripheral Processor) in a DP-PLL (Digital Processing-Phase Locked Loop), which is a basic clock generation unit consisting of triplexing among the network devices of an electronic switching system. (Telephony Device) relates to an interface method via a bus.

In the digital exchange, the basic clock generation unit of the synchronizer unit is used to generate a clock synchronized with the reference clock of the network.The phase detector, the digital to analog converter (DAC), the volume controlled X-tal oscillator (VCXO), and the Z-80A CPU DP-PLL is configured and operated. The microprocessor MGCP in the loop not only performs the synchronous function but also performs the triple operation, and donates the fault monitoring and troubleshooting for operation maintenance. In addition, it communicates with the PP through the TD bus and reports synchronization status information and fault information, and receives synchronization status change and related information from the PP.

The PP basically considers the unit that it wants to interface with via the TD bus. The TD bus with 11 signal lines provides one interrupt signal for interfacing with the embedded processor in the connected unit. This interrupt is triggered by a falling edge trigger. However, when multiple onboard processors are connected, one interrupt is used, so if any onboard processor is using an interrupt, the interrupt on the other onboard processor is ignored. This makes it difficult to use interrupts when multiple dual MGCPs are connected to the TD bus.

An object of the present invention is to provide a TD bus interface method of a network synchronizer in which MGCP configured to operate in such a triple operation enables an interface with a PP using a TD bus.

In order to achieve the above object, the present invention operates a basic clock generating unit in a triplex of an electronic switching device network device, and includes a processor MGCP (Master clock Generation Processor), a lower processor PP (Peripheral Processor), and a triple with PP. A TD bus interface method applied to a device including a TD (Telephony Device) bus for interfacing with a processor MGCP in the unit operated by a mobile phone; In order to transmit data from the MGCP to the PP, the MGCP checks whether the PP is normal when there is data to be transmitted to the PP; After performing the first step, if the PP is normal, first reading the first byte of the transmission buffer, and if the first byte is written as H'OO, the second step of transmitting and ending new information since the message is read from the PP; And if the first byte is not H'OO in the second step, check the first byte of the transmitter again after waiting for a predetermined time, and if the first byte does not become H'OO after a predetermined number of times, the PP is in an abnormal operation. Include a third step to record and finish.

In addition, the basic clock generating unit of the electronic switching device network device is operated in a triple, and the processor MGCP (Master clock Generation Processor) and the lower processor PP (Peripheral Processor) in the unit and the processor MGCP in the unit operated in the triple with the PP. A TD bus interface method applied to a device including a TD (Telephony Device) bus for interfacing with a device, the method comprising: a first step of confirming occurrence of a message reception interrupt in the MGCP when receiving data from the PP in the MGCP; After performing the first step, the MGCP reads the contents of the receiver and the MGCP reads the contents of the receiver and writes H'ff to the first byte of the receiver and checks the operation state record of the PP. 2nd step to finish; And after performing the first step, if the message is not received periodically, after waiting for a predetermined time, the PP is regarded as an abnormal operation state and includes a third step of finishing receiving the message from the MGCP.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a connection block diagram of the control processor MGCP in the DP-PLL of the network synchronizer and the TD bus of the PP.

Each MGCP0 (11) ((MGCP1 or MGCP2) (12, 13)) communicates with the PP 15 via the TD bus 14 to report synchronization related status information and fault information, and to change the synchronization status from the PP. And related information.

The TD bus 14 includes a clock, operation start signal (FS), mode / address 0 to 3 (MOD / ADDR0 to 3), receive data (RXD), transmit data (TXD), ready signal (RDY), and interrupt request signal. (IRQ), TD bus select signal TB_SEL, and TD bus error signal TB_ERR. FS signifies the start of operation of the TD bus 14 and is provided from the PP 15 to the MGCP0 11 ((MGCP1 or MGCP2) 12, 13). While FS is kept low, the operation mode such as read or write is sent through MOD0 ~ 3, and then the address signal is transmitted in 4 bit units through ADDR0 ~ 3. Receiving the mode and address, the MGCP0 11 ((MGCP1 or MGCP2) (12, 13)) decodes an address and sends an RDY signal to the PP 15. Upon receiving the RDY signal, the PP 15 sends or receives data in TXD or RXD. TB_SEL is a signal for selecting the TD bus 14 and a TB_ERR signal is generated when an error occurs on the bus.

FIG. 2 is a block diagram showing the TD bus interface portion of the MGCP0 11 ((MGCP1 or MGCP2) 12, 13) of FIG. 1, and the Z-80A CPU 21, the PP interface unit 22, and the RS422. It is composed of an interface unit 23, a memory 24 and an interrupt processing unit 25.

The Z-80A 21 is an 8-bit microprocessor as a central processing unit. The Z-80A 21 receives an interrupt through the interrupt processor 25 to read data from the memory 25 or to write data to the memory 24 if necessary. .

The memory 24 has a function of storing data and is composed of DPRAM (Dual Port Random Access Memory) so that reading and writing are possible at the same time. The memory area is divided into a transmitter and a receiver, and when data is received from the PP interface unit 22, data is temporarily stored in the receiver. In the case of writing data, the PP 15 and the Z-80A 21 of FIG. 1 have different CPUs, and different clocks are used. Therefore, the PP 15 and Z-80A 21 use a memory to write the clock used by the PP 15 of FIG. The written data is read by the Z-80A (21) as the clock stored by the Z-80A (21). When data is sent from the Z-80A 21 to the PP 15 of FIG. 1, the data is temporarily stored in the transmitter. At this time, data is written to the clock used by the Z-80A 21. The written content is read by the clock used by the PP 15 of FIG. 1 and sent to the PP interface unit 22.

The interrupt processor 25 receives the address of the transmitter of the memory 24 and generates an interrupt to the Z-80A 21 when the transmission data is 32 bytes. The contents of the 32 bytes of memory are all read by the Z-80A 21 and the interrupt is released.

The TD bus 14 of FIG. 1 first sends a mode signal for separating data to be read or written, and then transmits the address by dividing the address in units of 4 bits, and sends data to transmit a control signal. Accordingly, the PP interface unit 22 converts the data of the memory read by the clock provided by the PP 15 to the TD bus interface standard in parallel / serial order for communication between the PP 15 of FIG. 1 and the processor. Performs a function of transmitting to the RS-422 interface unit 23. In addition, a signal input from the RS-422 interface unit 23 generates a control signal for writing using a mode signal so that the memory 24 can write to the memory 24. And the data are written to the memory 24 by serial / parallel conversion.

The RS-422 interface 25 has the MGCP0 11 ((MGCP1 or MGCP2) 12, 13) of FIG. 1 and the PP 15 of FIG. Output data of the PP interface 22 when data is transferred from the (MGCP1 or MGCP2) (12, 13) to the PP 15 of FIG. 1 using the TD bus 14 of FIG. Is changed to RS-422 and transmitted to the TD bus 14 of FIG. Then, the data transmitted from the PP 15 of FIG. 1 to the TD bus 14 of FIG. 1 by RS-422 is converted into a TTL and transmitted to the PP interface 22.

3 is a block diagram showing the TD bus interface portion of the PP. Information for exchange with the PP from the device is input to the PPTDI 32 via the TD bus 31. The PP may be a PPTDI 32, a local bus 33, an MC68030 CPU 34, a ROM 35, an SRAM 36, a DRAM 37, an MFPI 38 (Multi Function Peripheral 1), an MEP 2 39, or the like. It is made up. The Peripheral Processor Telephony Device Interface (PPTDI) 32 provides the ability to interface between the TD bus and the PP. It is an on-demand semiconductor integrated into one 84-pin plastic leadless chip carrier (PLCC) for matching two TD buses. This PPTDI transmits and receives various signals on the TD bus, requests the MC68030 CPU 34 the interrupt generated by the hardware device, and provides the interrupt vector during the interrupt confirmation cycle.

FIG. 4 is a block diagram of the PP 15 of FIG. 1 centering on the TD bus interface. The MC68030 34, the local interface 32-2, the TD bus interface 32-1, and the interrupt processor are shown in FIG. It consists of (32-3).

The MC68030 34 is a 32-bit microprocessor as a central processing unit and detects the failure of the TD bus 14 of FIG. 1 by receiving and processing an interrupt signal from the interrupt processor 32-3. And receiving and processing status information of the MGCP0 11 ((MGCP1 or MGCP2) 12, 13) of FIG. 1 from the local interface unit 32, or the MGCP0 11 ((MGCP1 or MGCP2) of FIG. (12, 13)), the synchronization state change and related information are transmitted to the local interface unit 32-2.

The local interface unit 32-2 receives synchronization state change and related information for controlling the MGCP0 11 ((MGCP1 or MGCP2) 12, 13) of FIG. 1 from the TD bus interface unit 31. A read or write signal is generated by interpreting a MOD signal, and the address received in units of 4 bits is re-parallelized, and serial / parallel conversion of data received in series is performed to transmit the data to the MC68030 34. Then, the synchronization change of the MGCP0 11 ((MGCP1 or MGCP2) (12, 13)) of FIG. 1 is received from the MC68030 34 and related information. That is, MOD0 ~ 3 signals are generated by receiving a read or write signal, ADDR0 ~ 3 are generated to be transmitted in units of 4 bits by receiving addresses transmitted in parallel, and data is converted by parallel / serial conversion.

The interrupt processor 32-3 receives bus fault related information detected by the TD bus interface 31, drives various levels of interrupt signals according to the fault type, and transmits the interrupt signal to the MC68030 34.

The TD bus interface unit 31 receives mode, address, data, control signals, etc. from the local bus interface unit 32-2, changes the electrical characteristics for transmission in the RS-422 manner, and differentially performs the TTL differential. Transmit to TD bus 14 in FIG. In addition, the mode, address, data, and control signals are received from the TD bus 14 of FIG. 1 in the RS-422 manner, and are changed to the TTL level to be transmitted to the local bus interface 32-2. The TD bus detects a failure of the TD bus, and transmits a failure signal to the interrupt processor 33.

5 is a flowchart for transmitting data from the MGCP0 (11), the MGCP1 (12), and the MGCP2 (13) of the first diagram to the PP (15) of the first diagram.

The MGCP0 (11), MGCP1 (12) and MGCP2 (13) of FIG. 1 send DP-PLL status information to the PP (15) of FIG. 1 periodically, so that the MGCP0 (11) and MGCP1 (12) of FIG. ), You can check the operating status of the MGCP2 (13). MGCP0 (11), MGCP1 (12), and MGCP2 (13) of FIG. 1 confirm that the PP (15) of FIG. 1 is normal when there is data to be transmitted to the PP (15) of FIG. (42).

The status register is used to check whether the PP 15 of FIG. 1 is normal. In case of abnormality, the status register is set. If the contents of the status register are reset and the PP 15 of FIG. 1 is normal, first the first byte of the transmitter of the memory 24 of FIG. 2 is checked (43). If the first byte is written as H'OO, this means that a message has been read from the PP 15 of FIG. 1, so that 32 bytes of new information are stored (44) in the transmitter of the memory 24 of FIG. ). When writing data to the transmitter of the memory 24 of FIG. 2, H'7f is written in the first byte in the case of the MGCP0 (11) in FIG. 1, and in the case of MGCP1 (12) in FIG. In the case of MGCP2 (13) of FIG. 1, H'df is written. It sends the necessary information in 31 bytes except the first byte. If the first byte of the transmitter of the memory 24 of FIG. 2 is not H'OO, this means that the message has not been read from the PP 15 of FIG. 1 since the message has not been read yet. Check the first byte of the transmitter of (24) and try a certain number of times (46) If the first byte does not become H'OO, record that the PP 15 of FIG. 1 is performing abnormal operation (47) and finish (48). ).

FIG. 6 is a flowchart for receiving data sent by the PP 15 of FIG. 1 from the MGCP0 11, MGCP1 12, and MGCP2 13 of FIG. 1.

In the MGCP0 (11), MGCP1 (12) or MGCP2 (13) of FIG. 1, if a message reception interrupt occurs from the interrupt processing unit (25) of FIG. 2, it is checked (51) and the receiving unit of the memory (24) of FIG. Read the contents of (52). After reading the contents of the last 32 th byte, the interrupt is canceled by the interrupt processing unit 25 of FIG.

The MGCP0 (11), MGCP1 (12) or MGCP2 (13) of FIG. 1 reads the contents of the receiver of the memory 24 of FIG. 2 and writes H'ff to the first byte of the receiver (53). This is to inform the PP 15 of FIG. 1 that the content written in the previous state has been read. On the other hand, the operation state record of the PP 15 of FIG. 1 is checked (54). If abnormal, the H'OO is recorded in the status register to be corrected to the normal state (55). The MGCP1 12 or MGCP2 13 periodically monitors whether a message is received using an internal timer. If a message is not received periodically (56), after waiting a certain time (57), the PP 15 of FIG. 1 is regarded as an abnormal operating state (58), and the state leisurester is set and finished (59).

FIG. 7 is a flowchart for transmitting data from the PP 15 of FIG. 1 to the MGCP0 11, MGCP1 12, and MGCP2 13 of FIG. 1 in the PP 15 of FIG. If there is information to be sent to the MGCP0 (11), MGCP1 (12), and MGCP2 (13) of the diagram (61), the memory 24 of the second diagram of the relevant figure (MGCP0 (11), MGCP1 (12) or MGCP2 (13)) first Check the first byte of the receiver (62). If the contents of the first byte are H'ff (68), the related MGCP0 (11) (MGCP1 (12) or MGCP2 (13)) reads the previous state information normally, so new data is written and 32 bytes of data are finished. (64, 65). If the contents of the first byte of the receiver of the memory 24 of FIG. 2 of the related MGCP0 11 (MGCP1 12 or MGCP2 13) of FIG. 1 are not H'ff, the related MGCP0 of FIG. (11) (MGCP1 (12) or MGCP2 (13)) has not read data previously sent or an abnormal condition occurs in the related MGCP0 (11) (MGCP1 (12) or MGCP2 (13)) of FIG. If it is a case, wait for a predetermined time and check the receiving unit of the memory 24 of FIG. If the recovery is not continued for a certain number of times (67), the relevant MGCP0 (11) (MGCP1 (12) or MGCP2 (13)) of FIG. 1 is regarded as a failure state (68), and ends (65). In case of a fault state, the data transmitted by the MGCP0 (11), the MGCP1 (12), and the MGCP2 (13) of FIG. 1 to the PP (15) of FIG. Through the function received at (15), the data of the receiver of the memory 24 of FIG. 2 is not read until the MGCP0 11, MGCP1 12, and MGCP2 13 of FIG. 1 are normally restored. Transmission data in the PP 15 of FIG. 1 is received by the MGCP0 11, MGCP1 12, and MGCP2 13 of FIG. 1 as shown in FIG.

8 shows data transmitted from the MGCP0 (11), the MGCP1 (12), and the MGCP2 (13) of FIG. 1 to the PP (15) of FIG. 1 from the PP (15) of FIG. A flowchart for receiving.

The PP 15 in FIG. 1 periodically sends 71 data to be sent by confirming the transmitting section of the memory 24 in FIG. 2 of the MGCP0 11, MGCP1 12, and MGCP2 13 of FIG. Check if there is any (72). If the first byte of the transmitter of the memory 24 of FIG. 2 is not H'OO (73), the data of MGCP0 (11), MGCP1 (12), and MGCP2 (13) of FIG. The contents of the transmitter of (24) are read (74). After reading the contents of the transmitter, H'OO is written to the first byte of the transmitter (75) to inform MGCP0 (11) (MGCP1 (12) or MGCP2 (13)) of FIG. 1 that the message has been read.

Then, the record of the operation state register of the associated MGCP0 11 (MGCP1 12 or MGCP2 13) shown in FIG. 1 is read (76). If the contents of the operation status register are not normal, the correct state is recorded (77) and then finished (78). If the first byte of the transmitter of the memory 24 of FIG. 2 is H'OO (73), the MGCP0 11 (MGCP1 (12) or MGCP2 (13)) of FIG. 1 does not transmit information. Therefore, after waiting a certain time (79) and continuously reading the contents of the transmitter of the memory 24 of FIG. 2 (7a), if the first byte does not become H'OO, the PP 15 of FIG. 1 is abnormally operated. Record (7b) and finish (78).

As described above, the present invention provides data by interfacing the control processor of DP-PLL, which is a basic clock generating unit, which is composed of triplexing in PP and network unit unit through TD bus in all electronic switch and MGCP without using interrupt. It is effective to prevent loss of information and to enable reliable and efficient communication.

Claims (4)

The basic clock generation unit of the electronic switching device network device is operated in a triple system, and the processor MGCP (Master clock Generation Processor) and the lower processor PP (Peripheral Processor) in the unit and the processor MGCP in the unit operated in the triple with the PP A TD bus interface method applied to a device including a TD (Telephony Device) bus for performing the above method; In order to transmit data from the MGCP to the PP, the MGCP checks whether the PP is normal when there is data to be transmitted to the PP (41, 42); After performing the first steps 41 and 42, if the PP is normal, read the first byte of the transmission buffer, and if the first byte is written as H'OO, the second step of transmitting and ending new information since the message is read from the PP. (43, 44, 48); And if the first byte is not H'OO in the second step (43, 44, 48), after waiting for a predetermined time and checking the first byte of the transmitter again, if the first byte is not H'OO after a predetermined number of attempts, the PP And a third step (45 to 48) of recording and ending the abnormal operation of the TD bus interface method of the network synchronizer device. 4. The method of claim 1, wherein when the PP receives information sent from the MGCP to the PP, the PP periodically checks whether there are data to be sent by checking three transmission buffers in the loop. (71, 72); After performing the fourth steps 71 and 72, if the first byte of the transmitter is not H'OO, the contents of the transmitter are read and written as H'OO to the first byte of the transmitter. Fifth steps (73 to 76, 78) to finish after correcting recording; And after performing the fifth step (73 to 76, 78), if the first byte of the transmitter is H'OO, wait for a predetermined time and again check the first byte of the transmitter, and if the first byte does not become H'OO after a certain number of attempts, And a sixth step (73, 78, 79) to record and finish the abnormal operation of the PP. The basic clock generating unit of the electronic switching device network device is operated in a triple system and interfaces with the processor MGCP (Master clock Generation Processor) and the lower processor PP (Peripheral Processor) in the unit and the processor MGCP in the unit operated in the triplet with the PP. A TD bus interface method applied to a device including a TD (Telephony Device) bus for performing the above method; A first step (51) of confirming occurrence of a message receiving interrupt in the MGCP when receiving data from the PP in the MGCP; After performing the first step 51, the MGCP reads the contents of the receiver and the MGCP reads the contents of the receiver and writes H'ff to the first byte of the receiver and checks the operation state record of the PP. Second steps 52 to 55 and 59 for correcting and ending to normal; And after performing the first step 51, if a message is not received periodically, after waiting for a predetermined time, the third step (56 to 59) to regard the PP as an abnormal operation state and finish receiving the message at the MGCP. TD bus interface method in a network device comprising a. 4. The method of claim 3, further comprising: a fourth step (61, 62) of first checking a first byte of a receiver of a related MGCP when there is data to be sent from the PP to the MGCP; A fifth step (63, 64, 65) of writing 32-byte data and ending when the first byte is H'ff after performing the fourth step (61, 62); And if the content of the first byte is not H'ff after performing the fourth step (61, 62), wait for a while and then check the first byte of the receiver of the related MGCP again and try again a certain number of times. If not, further comprising a third step (65 to 68) of deeming the relevant MGCP to fail and finishing.