JPS6129242A - Communication control equipment - Google Patents

Abstract

PURPOSE:To reduce the hardware quantity by storing the reception data obtained after assembling and the error presence/absence information obtained in a frame reception mode to an FIFO memory when the frame of a high-level data link control means is received. CONSTITUTION:An assembling circuit 1 assembles the input serial data into the parallel data to output it to a switching circuit 3 and at the same time outputs the control information on the reception end of a flag showing the end of data assembly and the frame end to a control circuit 2. The circuit 2 monitors the idle state of a memory FIFO4 and also controls the circuit 3 according to the control information supplied to supply either one of control information on the parallel data, the end of flag reception, etc. to the FIFO4. The identification signal which decides whether the parallel data of the FIFO4 is equal to the control information or not is outputted to an interruption display circuit 5 together with the signal switch shows whether the effective information is stored in the FIFO4 or not. Then the circuit 5 outputs a read request to an external device 6 to take over the information stored in the FIFO4. Thus the device 6 takes over the data on the FIFO4 and reports the FIFO4 that the effective information is reduced by a piece.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to a communication control device, in particular, to receive bit serial data of a high level data link control procedure (HDLC procedure) from a line, assemble it, and transfer it to an external device as parallel data. The present invention relates to a communication control device.

(Prior Art) Conventional communication control devices assemble data from a line in order to receive a plurality of consecutive frames at high speed in the HDLC procedure, and then store the received data in different first-in, first-out memories (hereinafter referred to as FIFO) for each frame. Step 2 related to frame reception: Since the presence/absence information was stored in a register different from the FIFO, it was necessary to provide the number of IFOs up to the so-called outstanding frame number, and it was also necessary to provide the number of IFOs up to the so-called outstanding frame number. Since control is required, there is a drawback that the amount of hardware increases.

(Object of the invention) The object of the invention is to sequentially convert parallel data after assembly into
In addition to storing information in the IFO to clarify the identification and context between frames, the information at the time of frame reception completion determination is also stored in the same FIFO, thereby eliminating the above disadvantages and reducing the number of FIFOs to one. An object of the present invention is to provide a communication control device that uses only a small amount of hardware.

(Structure of the Invention) According to the present invention, one li'IFO is provided, and an HDLC
There is obtained a communication control device characterized in that when receiving a frame in a procedure, the received data after assembly and the error information at the time of frame reception are stored in the FIFO.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

The figure is a block diagram showing an embodiment of the communication control device of the present invention. In the figure, an assembly circuit 1 assembles serial data input via a connection line 7 into parallel data and outputs the parallel data to a connection line 9, and also notifies the control circuit 2 via a connection line 8 of completion of data assembly and the end of a frame. Outputs control information such as flag reception light. The control circuit 2 monitors the empty state of the FIFO 4 input through the connection line 12 and transmits data through the connection line 17 based on the control information such as the data assembly light and hook reception light input through the connection line 8. The switching circuit 3 is controlled to transfer any of the control information such as the parallel data input via the contact g99 and the flag reception light input via the connection line 10 to the FI via the connection line 11.
At the same time as input to FO4, input to FI via connection line 12.
Also instructs FO4 to fill up. The contents of FIFO4 are n+1 bits x when the parallel data is n bits.
It consists of m words, and the 1 bit is used to identify whether the parallel data is control information such as flag reception light, etc.
The bit identification signal is sent to the interrupt display circuit 5 via the connection line 14.
is output to. The interrupt water circuit 5 is connected to F via the connection line 13.
Interruption or reading to cause the external device 6 to retrieve the information stored in the FIFO 4 by inputting a signal indicating whether valid information is stored in the IFO 4 and the discrimination signal from the connection line 14. The request is output via the connection line 16. The external device 6 connects to the FIFO via the connection line 15.
At the same time as receiving the output data of 4, it reports to FIFO 4 via the connection line 18 that the number of valid information has decreased by one.

(Effects of the Invention) As is clear from the above explanation, the communication control device of the present invention receives high-speed consecutive bit serial data of a plurality of frames from a line using the HDLC procedure, and assembles the frame to an external device. In order to transfer the HEPA 2-rel data, it is sufficient to provide one FIFO and store assembled data and error presence/absence information at the time of frame reception in the FIFO, resulting in an effect of reducing the amount of hardware.

[Brief explanation of the drawing]

The figure is a block diagram showing an embodiment of the communication control device of the present invention. In the figure, 1...assembly circuit, 2...
Control circuit, 3...Switching circuit, 4...Fast toy first timer (FIFO), 5
...Interrupt display circuit, 6...External device,
7. ~16... Connection line. −′−・5

Claims (1)

[Claims] A communication control device comprising one first-in, first-out memory, and storing assembled received data and error presence/absence information at the time of frame reception in the first-in, first-out memory upon frame reception of a high-level data link control procedure. .