JPH03150943A - Communication equipment - Google Patents

Abstract

PURPOSE:To reduce the quantity of hardware by using a main memory in a protocol processing section also for a memory for forming a frame so as to eliminate the need for the memory for forming the frame at a cell reception section. CONSTITUTION:An FIFO management section 64 reads a data stored in data and address FIFOs respectively and writes the N-bit data stored in the data FIFO into a main memory 7 of a protocol processing section 70 directly from an interface section 65 according to the M-bit memory addresses stored in the address FIFO. Then frames for plural channels in the unit of 1 cell in the main memory 71 are formed. Since the main memory 71 in the protocol processing section 70 is used also as the memory for frame forming in this way, the frame forming memory is not required for the cell reception section 60 and the hardware quantity is reduced by the memory.

Description

[Detailed description of the invention] [Industrial field of application] Multi-channel cells (cells are
This relates to a communication device that transmits and receives fixed-length packets.

[Prior Art] FIG. 2 shows a conventional example of a communication device that transmits and receives cells to and from an ATM switch.

This communication device includes a cell receiving unit (BPAD) 10 that receives cells from an ATM switch, a cell transmitting unit (FPAD) 20 that sends cells to an ATV switch, and a protocol processing unit (PPR) 30 that performs protocol processing. The basic structure is

In FIG. 2, numeral 40 is a cell received from the ATM switch, 50 is a cell sent to the ATV switch, and these cells 40.50 each contain a header section containing header information and a cell containing other information. It consists of a data section containing information on the

The cell receiving unit 10 includes a buffer (CB) 11 that temporarily holds the cell 40, a header control unit (CTL) 12 that manages information in the header section of the cell 40, and processes the received cell as frame information. A frame forming memory (FM) 13 that forms frames for transmission, and a transmission frame buffer (B) that stores frame information to be transmitted.
F) 14 and the cell receiving section 10 as a protocol processing section 30
Processor bus interface section (I
NF) 15.

On the other hand, the protocol processing unit 30 has main memory (MM)
31, a DMA transfer unit 32 for speeding up the transfer,
The configuration includes a processor section (CPU) 33 and a memory bus 34, to which the interface section 15, header control section 12, and cell transmission section 20 are connected.

With the above configuration, the cell 40 received by the buffer 11 is first formed into a frame in the frame forming memory 13 based on the information in the header section in order to be processed as frame information of the corresponding channel.

When the frame formation in the frame formation memory 13 is completed, the processor section 33 operates the DMA transfer section 32 to transfer the frame information, and the frame information formed in the frame formation memory 13 is transferred via the interface section 15. The frame sent to the memory bus 34 is transferred to the main memory 31.

On the other hand, when the DMA transfer is completed, the processor section 33 notifies the header control section 12 that the block on the frame forming memory 13 in which the frame was stored is an empty block, and starts protocol processing for this frame. Now.

[Problem to be Solved by the Invention 1 However, in the above-mentioned conventional device, first the cell receiving unit 1
0 to form a frame, and then the protocol processing unit 3
Since the transfer process is performed by operating the DMA transfer unit 32 in 0, there is a problem in that the processing time from receiving a cell to performing protocol processing becomes long.

Furthermore, the frame forming memory 13 is indispensable in the cell receiving section 10, resulting in a problem that the amount of hardware increases.

Furthermore, since the memory bus 34 is used as a frame transfer path by the DMA transfer unit 32, the processor unit 33 is held in a held state during frame transfer processing, resulting in a problem that the processing capacity of the processor unit 33 is reduced. Ta.

This invention was proposed to solve the above-mentioned problems, and is a communication device that transmits and receives cells to and from an ATM switch. It is an object of the present invention to provide a communication device that can reduce the amount of hardware in a cell receiving section and that does not reduce the processing capacity of a processor section in a protocol processing section due to frame transfer processing. shall be.

[Means for Solving the Problems] A communication device according to the present invention includes a cell receiving section that receives cells from an ATM exchange, and a protocol processing section that performs protocol processing on cells received (M) by the cell receiving section as frame information. and a cell transmitting section that sends cells to the ATM switch, and transmits and receives cells on multiple channels to and from the ATM switch, and is characterized by the above-mentioned cell receiving section and protocol processing section. There is.

Specifically, the cell reception unit includes a data FIFO that stores cell data obtained by removing header information from received cell information in N-bit units, an M-bit memory address, and the last data of the frame. An address FIFO that can store an END bit indicating the
and a FIFO management section.

Here, the FIFO management section creates a memory address and an END bit to be stored in the address FIFO based on the header information of the cell received by the cell reception section, and sends it to the address FIFO. Furthermore, this FIF○ management unit controls the data and address FIF○ management units.
Controls reading and writing of IFO.

On the other hand, the protocol processing section is equipped with a main memory having a bit configuration of M bits for addresses and N bits for data, and a processor section having a predetermined function for protocol processing.

The N-bit data stored in the data FIFO is directly stored in the main memory of the protocol processing unit from the interface unit installed in the cell reception unit according to the M-bit memory address stored in the address FIFO. , the main memory is characterized in that a frame of multiple channels is formed in units of one cell.

[Operation] In the communication device according to the present invention, the FIF in the cell receiving section
FJF○ for data and F for address by O management section
The data stored in the IFO is read, and the N-bit data stored in the data FIFO is directly read from the interface unit installed in the cell receiving unit according to the M-bit memory address stored in the address FIFO. The data is stored in the main memory of the protocol processing section, and a frame of a plurality of channels is formed in each cell in this main memory, and the main memory of the protocol processing section is also used as a memory for frame formation.

Therefore, no memory for frame formation is required in the cell receiving section, and the amount of hardware can be reduced accordingly.

In addition, the cell data received by the cell reception section is directly transferred from the cell reception section's interface section to the main memory of the protocol processing section to form a frame, which is different from the conventional case where a memory bus was used as a transfer path. In comparison, there is no problem that the processor section in the protocol processing section is held for frame transfer processing and the processing capacity of the processor section is reduced.

In addition, the cell information received by the cell reception unit is stored in the data F
It is held by IF○ and address FIFO, and is sequentially transferred to the main memory of the protocol processing unit in parallel with the reception operation, allowing frame formation to proceed in units of cells and channel multiplexing. Compared to the conventional method in which a frame is formed in the section and then transferred to the protocol processing section, the processing time from receiving a cell to processing the protocol can also be shortened.

[Embodiment] FIG. 1 is a block diagram of an embodiment of a communication device according to the present invention.

The communication device of this embodiment transmits and receives cells of multiple channels to and from an ATM switch, and includes a cell receiving section (BPΔD) 60 that receives cells from the ATV switch, and a cell receiving section (BPΔD) 60 that receives cells from the ATV switch. A protocol processing unit (PPR) 70 performs protocol processing on the information as frame information.
and a cell transmitter (FPA) that sends cells to the ATM switch.
D) 80 as a basic configuration.

In FIG. 1, reference numeral 40 is a cell received from the ATM switch, and 50 is a cell sent to the ATV switch. It consists of a data section containing other information.

The cell receiving unit 60 includes a buffer (CB) 61 that receives cells 40 from an ATM switch and temporarily holds them, and a first F.
IFO section (DF) 62 and second FIFO section (AF) 6
3, a FIFO management section (CTL) 64, an interface section 65, and an END-0 section 66.

Here, the first FIFO unit 62 stores cell data (data part information) obtained by removing the header information from the information of the cell 40 received by the buffer 61 in units of N bits (N is a positive integer). FIFO and its management section.

The second FIFO section 63 inputs an M-bit (M is a positive integer) memory address and an END bit (1 bit) indicating that the data is the last data of the frame to the data FIFO.
It is composed of an address FIFO that can store each N-bit data stored in the address FIFO, and a management section thereof.

The FIFO management unit 64 stores the cell 4 received by the buffer 61.
0 header information, create a memory address and an END bit to be stored in the address FIFO for each N-bit data stored in the data FIFO, and send it to the address FIFO; It also controls reading and writing of the data and address FIFOs.

The interface section 65 has first and second FIFs.
The O sections 62 and 63 are stored in the main memory (M
M) It is directly connected to 71 and serves to send the data stored in the data FIFO and address FIFO to the main memory 71.

The END-Q unit 66 detects that the END bit is set when the data of the address FIFO is read by the FIFO pipe FJ unit 64, and stores the address information at that time. Then, the processor unit (CPU) 721 in the protocol processing unit 70 is notified.

On the other hand, the protocol processing unit 70 includes the main memory 71
, a processor section 72 , and a memory bus 73 .

Here, the main memory 71 has a bit configuration of M bits for addresses and N bits for data, a processor section 72 has a predetermined function for protocol processing, and a memory bus 73.
A FIFO management section 64, an END-Q 66, and a cell sending section 80 are connected to the .

Processing operations in the communication device of this embodiment are as follows.

All the information of the received cell 40 is held in the buffer 61, and the header information (head information) is stored in the FIF
The O management unit 64 is notified. Further, the cell data (data part information) excluding the header information is serial/parallel converted to the data width (N bits) of the main memory 71 and stored in the data FIFO of the first FIFO section 62. .

The FIFO management unit 64 analyzes the header information, creates an M-bit memory address that is the address on the main memory 71 where the information of this cell is to be stored, and stores the information in the second FIFO.
The IFO unit 63 sends the data to the FIFO for 3-less units.

The FIFO management unit 64 also stores the received cell 4.
Knowing from the header information that 0 is the last cell of frame information, the last bit of this cell data is set to the data F.
When storing in the IFO, set the END bit to be sent to the address FIFO to indicate that it is the final frame information, and at the same time set this END bit to the address FIFO.
Store it in.

Cell information is stored in each FIFO in synchronization with the received cell data and clock.
The reading by the FO management unit 64 is performed completely asynchronously with this clock.

And FI'FO for data and FIFO for address
If data is stored in both, the FIFO management unit 6
4 reads the data stored in each FIFO, and transfers the N-bit data stored in the data FIFO to the interface unit 6 according to the M-bit memory address stored in the address FIFO.
5 directly to the main memory 71 of the protocol processing unit 70.

Then, in this main memory 71, a frame of a plurality of channels is formed for each cell.

Note that when writing to the main memory 71, each F
If the END bit is set in the data read from the IFO, the memory address at this time is stored in END-Q66, and the processor unit 72 is notified that the frame formation on the main memory 71 has been completed. The processor section 72 reads this END-Q, learns which block of the main memory 71 has completed frame formation, and performs protocol processing.

Further, the processor unit 72 notifies the FIF◯ management unit 64 of the data block for which protocol processing has been completed in the main memory 71 as an empty block.

The FIF○ management unit 64 reuses the address notified as a free block as a memory address of a cell received by the buffer 61 thereafter.

As is clear from the above description, in the communication device of the embodiment, the main memory 71 in the protocol processing section 70 is also utilized as a memory for frame formation.

Therefore, the cell receiving section 60 does not require a memory for frame formation, and the amount of hardware can be reduced accordingly.

In addition, the cell data received by the buffer 6I of the cell receiving section 60 is directly transferred from the interface section 65 of the cell receiving section 60 to the main memory 71 of the protocol processing section 70 to form a frame, so that the memory bus is transferred. Compared to the conventional case in which the protocol processing section 70 is used as a communication channel, there is no problem that the processor section 72 in the protocol processing section 70 is held for frame transfer processing and the processing capacity of the processor section 72 is reduced.

Furthermore, information on cells received by the cell receiving section 60 is held in a data FIFO and an address FIFO, and is sequentially transferred to the main memory 71 of the protocol processing section 70 in parallel with the reception operation, so that one cell can be stored. Since frame formation can proceed in units of channels and by channel multiplexing, compared to the conventional method in which frames are formed in advance in the cell reception section and then transferred to the protocol processing section, protocol processing is performed after receiving cells. It is also possible to shorten the processing time.

[Effects of the Invention] As described above in detail, the communication device according to the present invention reads data stored in the data FIFO and the address FIFO by the FIFO management unit in the cell reception unit, and reads the data stored in the data FIFO and the address FIFO. The N-bit data stored in the address FIFO is directly stored in the main memory of the protocol processing unit from the interface unit installed in the cell reception unit according to the M-bit memory address stored in the address FIFO, and then transferred to the main memory of the protocol processing unit. The main memory in the protocol processing section is also used as a memory for frame formation.

Therefore, the cell receiving section does not require a memory for frame formation, and the amount of hardware can be reduced accordingly.

In addition, the cell data received by the cell reception section is directly transferred from the cell reception section's interface section to the main memory of the protocol processing section to form a frame, which is different from the conventional case where a memory bus was used as a transfer path. In comparison, there is no problem that the processor section in the protocol processing section is held for frame transfer processing and the processing capacity of the processor section is reduced.

In addition, the cell information received by the cell reception unit is stored in the data F
The data is stored in the IFO and address FIFO, and is sequentially transferred to the main memory of the protocol processing unit in parallel with the reception operation, allowing frame formation to proceed in units of cells and channel multiplexing. Compared to the conventional method, in which a frame is formed in a frame and then transferred to a protocol processing unit, the processing time from receiving a cell to performing protocol processing can also be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a communication device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional communication device. 40.50...Cell, 60...Cell receiving unit, 61...Buffer, 62...First
FIFO section, 63...Second FIFO section, 6
4... FIFO management section, 65... Interface section, 66... END-0 section, 70... Protocol processing section, ■...... Main memory, 2...processor section, 73...memory bus, 80...cell transmission section.

Claims (1)

[Scope of Claims] A cell receiving section that receives cells from an ATM switch, a protocol processing section that processes the cells received by the cell receiving section as frame information, and a cell transmitting section that sends cells to the ATM switch. A communication device configured to transmit and receive cells of multiple channels to and from an ATM switch, wherein the cell receiving unit stores data in units of N bits of cell data obtained by removing header information from received cell information. an address FIFO capable of storing an M-bit memory address and an END bit indicating that it is the last data of a frame for each N-bit data stored in the data FIFO; A memory address and an END bit to be stored in the address FIFO are created based on the header information of the cell, and the address FIFO is stored in the address FIFO.
FIF for data and address
Equipped with a FIFO management unit that controls reading and writing of O.
On the other hand, the protocol processing unit is equipped with a main memory having a bit configuration of M bits for addresses and N bits for data, and a processor unit having a predetermined function for protocol processing, and stores data in the data FIFO. The N-bit data stored in the address FIFO is directly stored in the main memory of the protocol processing unit from the interface unit installed in the cell reception unit, and is processed in units of one cell in this main memory. A communication device characterized in that it forms frames for multiple channels.