JPS61196353A - Multiplexing bus control system - Google Patents

Abstract

PURPOSE:To set variably the number of buses to be used among any devices and to optimize a system data transfer speed by mounting an expansion bus in parallel to a data bus and recognizing mutually the setting number of the expansion buses among respective devices through the data bus. CONSTITUTION:When a device B is requested for data transferring/receiving by a device A, if the device A side possesses a transferring/receiving buffer 2, a message 'the expansion bus has been used' is indicated on the bus bit length of a sending command row and transferred through a data bus 5. When the device B possesses a transferring/receiving buffer 4, the device B carries out the following data transferring/receiving operation using both the data bus and the expansion bus 6 at the same time. When not the transferring/ receiving buffer 4, said device B does not carry out the following data transferring/receiving operation, but indicates 'expansion bus does not exist' on the bus bit length of the sending status and also indicates 'data transferring/ receiving is impossible' on the terminal information. When the device A recognizes this indication, said device A indicates 'expansion bus 6 has been not used' on the bus bit length of sending command and restarts transferring using only the data bus 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a multiplexed bus control system, and in particular, the present invention relates to a multiplexed bus control system, and in particular, in data transfer control between arbitrary devices, the system data transfer rate is adjusted in accordance with the data processing capability unique to each device. The present invention relates to a multiplexed bus control method suitable for optimization.

[Background of the invention]

Typically when configuring a data transfer system.

The bus bit length is determined as a fixed length depending on the maximum system processing capacity. Therefore, when connecting a device with low processing capacity, the system bus bit length is fixed even though the data transfer capacity is low, so the disadvantage is that it cannot be connected to the system unless the maximum bus bit length is set. there were. In addition, as an example of a multiplexed bus control method that takes into account degenerate operation such as disconnecting the faulty bus system when Fa failure occurs in a data transfer system that performs multiplexed bus control, Japanese Patent Laid-Open No. 56 It is described in JP-67424.

However, since the bus bit length is fixed in this case as well,
One drawback is that it is not possible to set a multiplexed bus that is appropriate for the processing capacity unique to the device.

[Purpose of the invention]

The purpose of the present invention is to address several such conventional drawbacks and to provide a data transfer system between any devices.

The number of buses used between arbitrary devices can be set variably.

Another object of the present invention is to provide a multiplexed bus control method that can optimize the system data transfer rate.

[Summary of the invention]

In order to achieve the above object, the present invention provides a data transfer system between arbitrary devices having a transmission/reception port +R1 for controlling data transmission/reception via a data bus, in which one or more expansion buses are provided in parallel with the data bus. The present invention is characterized in that the number of buses used between any two of the devices is changed by a procedure in which the set number of expansion buses between the devices is mutually acknowledged via the data bus.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic configuration diagram of a data transfer system for explaining a multiplexed bus control method showing an embodiment of the present invention. Here, two types of equipment, MA and B, will be explained.

In FIG. 1, 1 to 4 are transmitting and receiving buffers, 5 is a data bus 26 is an expansion bus, and 7 and 8 are transmitting and receiving data W' product memories.

The device @A is a transmitting/receiving buffer l connected to the data bus 5.
It has a transmitting/receiving buffer 2 connected to an expansion bus 6 and a transmitting/receiving data storage memory 7 for storing data from the transmitting/receiving buffers γ1 and 2. Similarly, the transmitting/receiving buffer 3 connected to the data bus 5, the transmitting/receiving buffer 4 connected to the expansion bus 6, the transmitting/receiving buffer 3 . It has a transmission/reception data storage memory 8 that stores data from /I.

FIG. 2 is a conceptual diagram of a command sequence sent from device A to device B, with a bus bit length of 11. Operation command 12 that instructs writing/reading etc. to the device [B], start information 13 that instructs the start address etc. of the device [B]
The data is transmitted via the data bus 5 in this order.

FIG. 3 is a conceptual diagram of a status string from device i1B to device A, with a bus bit length of 11. Operation command 12. The data is transmitted via the data bus 5 in the order of start information 13, end information 14 displaying the end result, and the like.

Next, the operation shown in FIG. 1 will be explained using FIGS. 2 and 3. In this embodiment, the data bus 5 is 8 bits long, and two 8-bits long expansion buses 6 are provided as two expansion buses.

When device A requests data transmission/reception to device B, if device A has a transmission/reception buffer 2, the use of the expansion bus 6 is indicated in the bus bit length LI of the sending command string (1-, data bus 5). is transferred to device B via When the device B side has the transmission/reception buffer 4, the data transmission/reception operation subsequent to the first one is executed using both the data bus 5 and the expansion bus 6 simultaneously. During the above operation, if device B does not have the sending/receiving buffer 4, it does not execute the next data sending/receiving operation and the bus bit length of the sending status is 11.
Displays that the expansion bus 6 is absent, and displays data transmission/reception (n not possible) in the end information 14, and ends the process.

When the device A side recognizes the absence of the expansion bus 6 from the device B, it indicates that the expansion bus 6 is not used in the bus bit length 11 of the sending command, and restarts data transmission and reception using only the data bus 5. On the other hand, when the device A side does not have the transmit/receive buffer 2, in order to indicate whether the expansion bus 6 is used in the bus bit length 11 of the sending command string, Data transmission/reception will be performed using only 5.

In this way, according to this embodiment, in a data transfer system between arbitrary devices, the connection bus bit length between devices can be controlled by device-specific processing within a range that does not exceed the maximum bus bit length based on the system processing capacity. Since it can be set arbitrarily according to the capacity, it is possible to optimize the data transfer rate according to the processing capacity of the device being executed during the data transfer processing operation of each device.

〔Effect of the invention〕

As explained above, according to the present invention, in a data transfer system between arbitrary devices, the number of buses used between arbitrary devices can be variably set, and the system data transfer speed can be optimized. A multiplexed bus control method can be realized.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a multiplexed bus control system showing one embodiment of the present invention, FIG. 2 is a conceptual diagram of a command sequence transferred from device A, and FIG. 3 is a conceptual diagram of a command sequence transferred from device B. FIG. 2 is a conceptual diagram of a status column. 1 to 4: transmission/reception buffer, 5: data bus, 6: expansion bus, 7.8: transmission/reception data storage memory, 11 bus bit length, 12 operation command, 13: start information, 14: end information. Figure 1

Claims (1)

[Claims] (1) In a data transfer system between arbitrary devices having a transmitting/receiving circuit that controls data transmission and reception via a data bus, one or more expansion buses are provided in parallel with the data bus, and an expansion bus between each device is provided. A multiplexed bus control system characterized in that the number of buses used between any of the devices is changed by a procedure of mutually recognizing the set number of devices via the data bus.