JPH09237258A - Computer system and fault informing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fault informing method which can speedily give information on a fault, can prevent the supply of a new job to a node where the fault occurs and can analyze the fault in short time. SOLUTION: In a computer system provided with an interface cross bar switch device connecting plural nodes, the respective nodes are provided with Sync pattern generation suppression circuits 105 suppressing the generation of Sync patterns when the fault occurs, storage timing control circuits 205 which do not generate data storage timing signals when the Sync patterns cannot be detected on a reception side and storage timing signal monitor circuits 280 detecting the absence of the data storage timing signals on the reception side. The generation of the Sync pattern is suppressed when the fault occurs on a transmission side. The interface cross bar switch device detects the occurrence of the fault when the Sync pattern cannot be detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer.
The present invention relates to a computer system configured by connecting a plurality of nodes as nodes through an interface crossbar switch, and a failure notification method in the computer system.

[0002]

2. Description of the Related Art With a supercomputer as one node,
A computer system is used in which a plurality of nodes are connected by an interface crossbar switch to enable data transfer between the nodes. FIG. 3 illustrates one node and an interface crossbar switch.

Data to be transferred, which is read from the main storage device (memory) of each node, is supplied to the optical signal transmission circuit 130 via the buffer 120. In addition, the Sync pattern generation instruction circuit 110, for example, at every predetermined clock,
A Sync pattern generation instruction signal is output to the optical signal transmission circuit 130 every 65 clocks. Optical signal transmission circuit 130
In accordance with the Sync pattern generation instruction signal, inserts synchronization control data called Sync pattern (synchronization pattern) into the data to be transferred at every predetermined clock. The interface crossbar switch and the nodes are connected by n optical cables 400. Since one optical cable controls 1-byte width data, n bytes of data can be transferred at one time.

The optical signal receiving circuit 200 of the interface crossbar switch detects the Sync pattern included in the data supplied via the optical cable 400 once every predetermined clock, and thereby, the optical signal receiving circuit 200 communicates with the transmitting side node. Make sure they are in sync. Optical signal receiving circuit 2
00 is, while correctly detecting the Sync pattern,
The reception data is supplied to the buffer 220, a data storage timing signal for storing the reception data in the buffer 220 is generated, and the buffer control circuit 210 is notified. The buffer control circuit 210 controls the buffer 220 according to the data storage timing signal and writes the data from the optical signal receiving circuit 200 to the buffer 220. The data stored in the buffer 220 is stored in the register 250, then transferred to the receiving side node via the crossbar switch circuit 255 via an optical fiber (not shown), and stored in the memory of the receiving side node.

In FIG. 3, a fault occurring in each node is detected by the fault detection circuit 100, and the node stops the transmission process. Furthermore, the fault detection circuit 100
Notifies the failure processing device 140 of the details of the failure. The failure processing device 140 displays the content of the notified failure on the signal line 34.
0 to the service processor 150 of the corresponding node.

The service processor 150 communicates the failure content to the service processor 260 of the interface crossbar switch via the optical cable 410. When the service processor 260 receives the failure content, the failure processing device 270 of the interface crossbar switch.
Notify.

In response to this notification, the failure processing device 270 interrupts the operating system (hereinafter referred to as "OS") 280 that controls the receiving node to notify the occurrence of the failure.

The OS 280 performs fault processing and notifies the fault content to the fault detection circuit 240 via the fault processing unit 270 of the interface crossbar switch. When the failure detection circuit 240 is notified of a failure, the operation of the interface crossbar switch is stopped.

[0009]

As described above, in the conventional system, when a failure occurs in each node, each node interrupts the control of the optical communication and notifies the failure processing device 140 of the occurrence of the failure. To do. The failure processing device 140 notified of the failure passes through the OS through the service processor 150 of the node, the service processor 260 of the interface crossbar switch 400, and the failure processing device 270.
280 had been notified of the failure.

For this reason, the OS2
There is a problem that the fault notification route up to 80 is long.

Also, in general, the fault handling devices 140, 27.
0 and the service clocks of the service processors 150, 260 are lower than the operation clocks of the nodes and the interface crossbar switch itself, and the operating speed is slower than that of the interface crossbar switch. Furthermore, the optical cable 4 connecting between the service processors 150 and 260
Since only one 10 is provided, it takes time to convert the parallel data / serial data of the data notifying the failure.

As a result, there is a problem in that it takes a huge amount of time to notify the failure, the failure notification to the OS 280 is delayed, and a new job (JOB) is submitted to the failed node. Also, it took a lot of time to analyze the failure.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a computer system and a failure notification method capable of promptly issuing a failure notification.

[0014]

In order to achieve the above object, a computer system of the present invention comprises a computer as one node, and a plurality of nodes are connected through an interface device. Each node is a transmission target. Data generation means for generating data, synchronization pattern generation means for generating a synchronization pattern for controlling the transmission timing of the data generated by the data generation means, failure detection means for detecting the occurrence of a failure, and the failure A synchronization pattern generation inhibiting circuit that controls the synchronization pattern generation means to inhibit generation of the synchronization pattern when a failure is detected by the detection means, transmission target data generated by the data generation means, and the synchronization pattern The synchronization pattern generated by the generation means is transmitted to another node via the interface device. The interface device includes a receiving means for receiving data from a transmitting side node, and a synchronization pattern in the data received by the receiving means, and the received data according to the detected synchronization pattern. Transfer means for transferring the data to the receiving side node, and when the synchronization pattern cannot be detected in the data received by the receiving means, the data transfer is interrupted and the receiving side node has a failure in the transmitting side node. And a control means for notifying of.

The transfer means, for example, means for generating a storage timing signal from a synchronization pattern in the data received by the receiving means, and means for storing the data received by the receiving means in accordance with the storage timing signal, The control means detects that a failure has occurred in the transmission side node when the storage timing signal matches a predetermined pattern.

The fault notifying method of the present invention is a fault notifying method in a computer system in which a plurality of computers are coupled via an interface device and data transfer between the computers is synchronized by a synchronization pattern. When a failure occurs, the sending computer stops generating the synchronization pattern, and the interface device determines that the failure has occurred in the computer when the synchronization pattern cannot be detected in the transmission data of the computer. Is notified to the data receiving computer of the occurrence of the failure.

According to the computer system and the failure notification method having such a configuration, when a failure occurs in each node, the synchronization pattern generation inhibiting circuit stops the generation of the synchronization pattern. Therefore, the interface device cannot detect the synchronization pattern in the received data,
It detects that a failure has occurred in the sending node and notifies the receiving node of the failure. Therefore, the fault occurrence node notifies the interface device of the fault occurrence at high speed through the original data transfer route.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to FIGS.

As shown in FIG. 2, the computer system of this embodiment has a supercomputer as one node and a plurality of nodes connected by an interface crossbar switch. The interface crossbar switch has a function of receiving data from the node and a function of receiving the data from the crossbar switch circuit 255.
It has a function of transmitting to another node via.

FIG. 1 shows the structure of one node and the interface crossbar switch for one node (broken line part in FIG. 3). In FIG. 1, a fault detection circuit 100 is a circuit that detects a fault occurring in a node. Sync
The pattern generation suppression circuit 105 receives the fault notification from the fault detection circuit 100, and the Sync pattern generation instruction circuit 1
This is a circuit for suppressing 10 Sync pattern generation instructions.

The Sync pattern generation instruction circuit 110 is
This circuit instructs the optical signal transmission circuit 130 to generate a Sync pattern once every 65 clocks.

The buffer 120 stores data to be transmitted from the memory, and stores the stored data in first-in
It is a circuit for outputting to the optical signal transmission circuit 130 by the first-out control.

The optical signal transmission circuit 130 includes a buffer 120.
After converting the parallel transfer data from the serial data into serial data, the electric signal is converted into an optical signal and output.
When the c pattern generation instruction circuit 110 is instructed to generate a Sync pattern, it is a circuit that stops receiving data from the buffer 120 and outputs the Sync pattern as an optical signal. In addition, the optical signal transmission circuit 130
When sending data, the EC
Generate C (Error Correcting Code) and transfer. In this embodiment, the S8EC-D8ED code is used to enable 1-byte error correction / 2-byte error detection. The node on the receiving side performs 1-byte error correction / 2-byte error detection from the received data and can correct even if the received data causes a 1-byte error.

The failure processing device 140 is a device for processing a failure in a node. Also, the service processor 150
Is a device that communicates with the service processor 260 of the interface crossbar switch.

The optical signal receiving circuit 200 converts the received optical signal into an electrical signal, converts serial data into parallel data and outputs the parallel data, and when receiving the Sync pattern, the storage timing control circuit 205 receives the Sync pattern. Is a circuit for notifying that the is received.

The storage timing control circuit 205 is a circuit for controlling the storage timing signal in response to the Sync pattern reception notification from the optical signal receiving circuit 200.

The buffer control circuit 210 includes a buffer 22.
This is a circuit for controlling 0. The buffer 220 receives the data from the optical signal receiving circuit 200 and the buffer control circuit 2
It is a buffer which is stored under the control of 10.

The storage timing signal monitoring circuit 230 monitors a total of n storage timing signals output from each storage timing control circuit 205, and when the state of all "0" continues for 2T or more, a failure occurs in the failure detection circuit 240. Is a circuit for notifying.

The fault detection circuit 240 is an interface
It is a circuit that detects a failure that occurs in the crossbar switch device. The register 250 is a register that stores data from the buffer 220. The crossbar switch circuit 255 is a circuit that outputs the data from the register 250 to the designated node. Service processor 26
Reference numeral 0 is a device that communicates with the service processor 150 of the node via the optical cable 410.

The fault processing unit 270 has an interface
A device for handling a fault in the crossbar switch device. The OS 280 has an interface with the upper node.
It is the OS of the opposite node (reception side node) connected via the crossbar switch device.

Next, normal data transfer in the above-mentioned configuration will be described. Data to be transmitted from the memory of the transmission side node is stored in the buffer 120 and is transmitted to the optical signal transmission circuit 130 via the signal line 320. Sy
The nc pattern generation instruction circuit 110 outputs 1 every 65 clocks.
The Sync pattern generation instruction signal is generated at the rate of the number of times and sent to the n optical signal transmission circuits 130 via the signal line 310.

Upon receiving the Sync pattern generation instruction signal, the optical signal transmission circuit 130 inserts the Sync pattern between the data from the buffer 120.

The optical signal transmission circuit 130 includes a buffer 120.
Data from SYNC and Sync inserted once every 65 clocks
The pattern and the pattern are sequentially converted from parallel data to serial data, and then converted from an electric signal to an optical signal and transmitted to the optical signal receiving circuit 200 of the interface crossbar switch via the optical cable 400.

The optical signal receiving circuit 200 converts the received optical signal into an electrical signal, then converts the serial data into parallel data, and buffers 220 via the signal line 510.
Send to

Further, if the received data is the Sync pattern, the optical signal receiving circuit 200 notifies the storage timing control circuit 205 via the signal line 500 that the Sync pattern has been received. When the Sync pattern is garbled due to noise or the like, the Sync pattern cannot be detected, the garbled byte becomes out of synchronization, and the data becomes invalid. However, if there is only 1 byte that causes data corruption, 1-byte error remains until the next Sync pattern is received, but normal data can be output by 1-byte error correction to continue the operation. it can.

The storage timing control circuit 205 uses Syn
When the reception of the c pattern is notified, 6 from the next clock.
Generate data storage timing signal for 4 clocks,
The buffer control circuit 210 and the storage timing signal monitoring circuit 230 are notified via the signal line 505.

The buffer control circuit 210 notified of the storage timing signal instructs the buffer 220 to store the data sent via the signal line 510. In addition, the n buffer control circuits 210 store the data in the register 250 via the signal line 530 when confirming that the data is completely stored in the n buffers 220 due to the byte synchronization, and the crossbar switch 210 The data is output to the memory of another node via the circuit 255.

When the optical signal receiving circuit 200 cannot receive the Sync pattern, the storage timing control circuit 205
Determines that the devices are not synchronized, stops the generation of the storage timing signal, and controls not to store the data in the buffer 220.

Next, the fault notification method of this embodiment will be described. When a failure occurs in the node, the failure detection circuit 100 detects it and notifies the Sync pattern generation suppression circuit 105 of the failure occurrence via the signal line 300.

The Sync pattern generation inhibiting circuit 105
When notified of the occurrence of a failure, the sync pattern generation instruction circuit 110 is instructed to suppress the generation of the sync pattern.
By this instruction, the Sync pattern generation instruction circuit 11
0 suppresses the output of the Sync pattern generation instruction signal and stops all the operations in the node.

The optical signal receiving circuit 200 cannot receive the Sync pattern, and the n storage timing control circuits 205 stop generating the storage timing signals. Therefore, all the storage timing signals are at "0" level.

The storage timing signal monitor circuit 230 stores the storage timing signal n sent via the signal line 505.
If all the books become "0" for 2T or more, it is determined that the device on the other side (in this case, the node) has failed,
The fault is notified to the fault detection circuit 240 via the signal line 540. When the Sync pattern cannot be received due to garbled data or the like, it is possible to distinguish from the suppression of the Sync pattern for indicating a failure by performing error correction using ECC.

When the fault detection circuit 240 detects a fault, the fault detection circuit 240 notifies the fault processing device 270 of the fault via the signal line 550 and stops the operation of the interface crossbar switch device.

The fault processing unit 270 interrupts the OS 280 of the receiving node via the signal line 570 to notify the occurrence of a fault.

In this way, in this embodiment, when a failure occurs on the transmitting side, all bytes of the Sync pattern inserted once every 65 clocks are forcibly suppressed, and the receiving side receives data of all bytes. The occurrence of a failure is detected by detecting that the storage timing signal is all 0 for 2T or more.

By providing the circuit having the above-described configuration, it becomes possible to notify the OS 280 of the occurrence of the failure in a short time because the failure can be notified through the transmission path of the normal data transfer. Therefore, a new job is not submitted to the node after the occurrence of a failure, and since the wasteful operation is not performed, the failure analysis is facilitated.

The present invention is not limited to the above embodiment. For example, in the above embodiment, an example in which a plurality of nodes are connected by the interface crossbar switch is shown, but it is possible to connect using any other interface device. Also, the insertion timing of the Sync pattern may be other than once every 65 clocks.

[0048]

According to the present invention, when a failure occurs on the transmission side, the sending of the synchronization pattern is suppressed, and when the reception side cannot detect the synchronization pattern, the failure on the transmission side is detected. can do.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 100 Fault Detection Circuit 105 Sync Pattern Generation Suppression Circuit 110 Sync Pattern Generation Instruction Circuit 120 Buffer 130 Optical Signal Transmission Circuit 200 Optical Signal Reception Circuit 205 Storage Timing Control Circuit 210 Buffer Control Circuit 220 Buffer 230 Storage Timing Signal Monitoring Circuit 240 Fault Detection Circuit 250 Register 255 Crossbar switch circuit 300, 340 Signal line 400, 410 Optical cable 500, 570 Signal line

Claims (3)

[Claims] 1. A computer system comprising a computer as one node and a plurality of nodes connected to each other through an interface device, wherein each node generates data to be transmitted, and data generation means, and the data generation means. Pattern generation means for generating a synchronization pattern for controlling the transmission timing of the generated data, failure detection means for detecting the occurrence of a failure, and synchronization pattern generation means for detecting a failure by the failure detection means A synchronization pattern generation suppressing circuit for controlling the means to suppress the generation of the synchronization pattern, the transmission target data generated by the data generating means, and the synchronization pattern generated by the synchronization pattern generating means to another node to the interface device. Transmitting means for transmitting via the interface, And a receiving means for receiving data from the transmitting side node, and a transfer means for detecting a synchronization pattern in the data received by the receiving means and transferring the received data to the receiving side node according to the detected synchronization pattern. And a control means for interrupting the data transfer and notifying the receiving side node that a failure has occurred at the transmitting side node when a synchronization pattern cannot be detected in the data received by the receiving means. A computer system characterized by the above. 2. The transfer means generates a storage timing signal from a synchronization pattern in the data received by the reception means, and stores the data received by the reception means according to the storage timing signal.
2. The computer system according to claim 1, wherein the control means detects that a failure has occurred in the transmission side node when the storage timing signal matches a predetermined pattern. 3. A failure notification method in a computer system in which a plurality of computers are coupled via an interface device and data transfer between the computers is synchronized by a synchronization pattern, wherein the computer on the data transmission side has a failure. When it occurs,
The generation of the synchronization pattern is stopped, and the interface device determines that a failure has occurred in the computer when the synchronization pattern cannot be detected in the transmission data of the computer, and notifies the computer on the data receiving side of the occurrence of the failure. A failure notification method characterized by: