JP3160927B2 - Loop test circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a loop test circuit, and more particularly, to a loop test circuit that loops back a data signal from a host device.

[0002]

2. Description of the Related Art Conventionally, in this type of loop test circuit, as shown in FIG. 2, when a loop control bit separation circuit 3 detects a loop control bit in a control signal from a higher-level device (not shown), the loop control The bit separation circuit 3 outputs a loop switch circuit control signal 101 and a state bit multiplex circuit control signal 102 to the loop switch circuit 1 and the state bit multiplex circuit 2, respectively. Upon receiving the loop switch circuit control signal 101 from the loop control bit separation circuit 3, the loop switch circuit 1 transmits a data signal from a higher-level device to a terminal device (not shown), and transmits a data signal from the terminal device to the higher-level device. Is switched from a normal communication state transmitted to the host device to a test state in which a data signal from the host device is returned to the host device. The state bit multiplexing circuit 2 receives the state bit multiplexing circuit control signal 10 from the loop control bit separating circuit 3.
When 2 is received, the status bits for notifying the host device that the instruction for loop control has been received are multiplexed. That is, the status bit multiplexing circuit 2 has transmitted the status bits to the host device regardless of whether the loop switch circuit 1 operates normally.

In such a conventional loop test circuit, the status bits are transmitted from the status bit multiplexing circuit 2 to the host device regardless of whether the loop switch circuit 1 operates normally. There is a problem that the abnormality of the loop switch circuit 1 cannot be detected until it is detected that the data signal is not looped back from the loop switch circuit 1. In addition, even if the host device detects that the data signal is not looped back from the loop switch circuit 1, there is a problem that the location where the abnormality has occurred cannot be specified.

[0004]

SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned problems of the prior art, and can detect an abnormality in a loop switch circuit at an early stage, and can specify a place where an abnormality has occurred. The purpose of the present invention is to provide a loop test circuit.

[0005]

A loop test circuit according to the present invention controls a loop switch circuit and receives an instruction for loop control when a loop control bit is received from a host device.
A status bit for notifying the host device of the
A loop test circuit for sending a signal to the host device ,
The status bit is transmitted to the host device via the loop switch circuit.

[0006]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, when a loop control bit separation circuit 3 detects a loop control bit in a control signal from a higher-level device (not shown), the loop control bit separation circuit 3 sends a loop switch to a loop switch circuit 1 and a state bit multiplexing circuit 2 respectively. A circuit control signal 101 and a state bit multiplex circuit control signal 102 are output.

When the loop switch circuit 1 receives the loop switch circuit control signal 101 from the loop control bit separation circuit 3, it transmits a data signal from a higher-level device to a terminal device (not shown), and a data signal from the terminal device. Is switched from a normal communication state in which is transmitted to the host device to a test state in which a data signal from the host device is returned to the host device.

The state bit multiplexing circuit 2 is provided between the loop switch circuit 1 and the loop control bit separation circuit 3, and receives a state bit multiplexing circuit control signal 102 from the loop control bit separation circuit 3; A status bit for notifying the host device that the instruction for the loop control has been received is multiplexed into a signal from the loop control bit separation circuit 3 to the loop switch circuit 1. Therefore, when the loop control bit separation circuit 3 detects the loop control bit in the control signal from the host device and the loop switch circuit 1 operates normally, the status bits are multiplexed by the status bit multiplexing circuit 2. The signal is looped back from the loop switch circuit 1 to the host device. On the other hand, if the loop switch circuit 1 does not operate normally, the signal in which the status bits are multiplexed by the status bit multiplexing circuit 2 is not returned from the loop switch circuit 1 to the host device.

As described above, the status bit multiplexing circuit 2 is provided between the loop control bit separation circuit 3 and the loop switch circuit 1, and the status bits from the status bit multiplexing circuit 2 are transmitted to the host device via the loop switch circuit 1. By transmitting the data, when an error occurs in the loop switch circuit 1 and the data signal from the host device cannot be turned back, the status bit from the status bit multiplexing circuit 2 is not transmitted to the host device. Therefore, an abnormality of the loop switch circuit 1 can be detected at an early stage, and the location where the abnormality has occurred can be specified. That is, if the status bit from the status bit multiplexing circuit 2 is not transmitted to the higher-level device, the higher-level device determines that the loop switch circuit 1 is abnormal or the transmission path between the higher-level device and the loop switch circuit 1 is abnormal. Can be.

[0011]

As described above, according to the present invention, a status bit for notifying a higher-level device that a loop control bit has been received from a higher-level device is transmitted to a higher-level device via a loop switch circuit. By doing so, the abnormality of the loop switch circuit can be detected early,
There is an effect that it is possible to specify the location where the abnormality has occurred.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Loop switch circuit 2 State bit multiplexing circuit 3 Loop control bit separation circuit

Claims (1)

(57) [Claims] 1. A upon receiving the loop control bit from the host device, Lou controls the loop switch circuit
Notification to the host device that the
What is claimed is: 1. A loop test circuit for transmitting a status bit to be notified to said host device , wherein said status bit is transmitted to said host device via said loop switch circuit.