JPS6121695Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a central processing unit, and particularly to a microprogram-controlled central processing unit.

A conventional central processing unit has a control memory section that stores a microprogram consisting of microprogram words to which ECC bits are added, and an address section that stores an address for reading the microprogram word from the control memory section. and a holding section for holding the microprogram word read out from the control storage section; and an ECC check of the microprogram word held in the holding section, and when there is a 1-bit error, the error bit is automatically corrected and the 1-bit error is detected. A check section that outputs an instruction signal and outputs an error instruction signal of 2 or more bits when there is an error of 2 bits or more, and a microprogram word output from the holding section and a microprogram after 1-bit error correction output from the check section. A selection section which switches the word depending on whether or not a 1-bit error instruction signal is supplied, and a microprogram word output from the selection section determines the next address of the microprogram and controls the clock according to the error signal from the check section. Logic that outputs a clock delay signal that instructs the clock to delay the output timing of the supplied clock signal when there is a 1-bit error, and outputs a clock stop signal that instructs the clock to stop when there is an error of 2 or more bits. The clock section supplies a clock signal to the address section, the holding section, and the logic section.

Examples of conventional central processing units will be described in detail below with reference to the drawings.

Figure 1 is a block diagram showing an example of a conventional central processing unit.
A control storage section 2 stores a microprogram consisting of a microprogram word to which bits are added; an address section 1 stores an address for reading out the microprogram word stored in the control storage section 2; Microprogram language 1
2, and a check section 4 that performs an ECC check of the microprogram word 13 held in the holding section 3 and automatically corrects 1-bit errors.
, a selection section 5 which selects either the microprogram word 13 or the microprogram word 14 whose 1-bit error has been automatically corrected by the check section 4 and outputs it as the microprogram word 15; and a logic section operated by the microprogram word 15. 6 and
It consists of the address section 1, a clock section 7 which supplies clocks to the holding section 3 and logic section 6.

Clock signal 103 is sent to address 16 in logic section 6.
The clock signal 104 is output from the clock section 7 at the timing when the clock signal 103 is output, and after the address section 1 gives the address 11 to the control memory section 2, the clock signal 104 is a microprogram read from the control memory section. The clock unit 7 outputs the signal at the timing when the word 12 is determined.

However, since the memory element used in the control memory section 2 has the characteristic that the access time gradually becomes slower over time and a permanent failure occurs, the memory element used in the control memory section 2 has a characteristic that the access time gradually becomes slower as the time goes by and a fixed failure occurs. The fixed bit or the fixed fault bit is the bit that is erroneous.
It will be set to .

The microprogram word 13 set in the holding section 3 is subjected to an ECC check in the check section 4. If there is a 1-bit error, an error instruction signal 101 is sent to the selection section 5 and the logic section 6, and the selection section 5 detects a 1-bit error. In response to the instruction signal 101, the microprogram word 14 is outputted to the logic section 6 as the microprogram word 15.

When the logic unit 6 receives the 1-bit error instruction signal 101, the microprogram word 14 with the error bits of the microprogram word 13 corrected is determined for the clock unit 7, and is sent to the logic unit 6 as the microprogram 15 that has passed through the selection unit 5. The clock delay signal 106 is outputted to the clock section 7 so that the clock signal 105 is delayed until the clock signal 105 is sent correctly and the operation of the logic section 6 is completed normally.

Furthermore, when there is an error of 2 or more bits, a 2 or more bit error indication signal 102 is output, and the logic section 6 operates to output a clock stop signal 107, thereby stopping the central processing unit.

Therefore, in the conventional central processing unit, the performance of the central processing unit decreases when there is a 1-bit error, and the performance of the central processing unit decreases when there is a 1-bit error.
The drawback was that the system would go down if an error occurred with more than one bit.

In other words, conventional central processing units prevent errors by delaying the clock signal to a certain extent even if access delays occur in the control storage unit over time; The drawback was that if a delay occurred, an error would occur and the system would go down.

SUMMARY OF THE INVENTION An object of the present invention is to provide a central processing unit that can detect delays in accessing a control storage unit at an early stage so that the control storage unit can be easily replaced in advance to prevent system failure.

That is, an object of the present invention is to provide a central processing unit that can reduce the frequency of performance deterioration or system down when an error occurs when the central processing unit reads a microprogram word from a control storage unit.

The central processing unit of the present invention includes a control memory section that stores a microprogram consisting of microprogram words to which ECC bits are added, and an address that stores an address for reading the microprogram word from the control memory section. a holding section for holding the microprogram word read out from the control storage section; performing an ECC check on the microprogram word held in the holding section and automatically correcting the error bit in the case of a 1-bit error; A check section that outputs a 1-bit error indication signal and outputs a 2-bit or more error indication signal when there is an error of 2 bits or more, and a microprogram word output from the holding section and 1-bit error correction output from the check section. a selection section that switches the next microprogram word in response to a 1-bit error instruction signal; and a selection section that operates based on the microprogram word output from the selection section, further determines the next address of the microprogram, and selects the next address of the microprogram according to the error signal from the check section. When there is a 1-bit error, a clock delay signal is output that instructs the clock section to delay the output timing of the supplied clock signal.
A logic section that outputs a clock stop signal to instruct clock stop in the event of an error of more than one bit; a clock section that supplies a clock signal to the address section, the holding section, and the logic section; and a timing section held by the holding section. A holding circuit that holds the microprogram word read out at an earlier timing; and a check circuit that performs an ECC check on the microprogram word held by the holding circuit and sends an error signal to the logic section when the check results in an error. and an address holding circuit that holds the address when the error signal is supplied.

In other words, the central processing unit of the present invention includes a holding circuit that holds a microprogram word at a timing earlier than that of a holding section, and a logic section that performs an ECC check of the microprogram held in this holding section, and when an error is detected as a result of the check. By adding a check circuit that generates an error signal to notify the control memory and an address holding circuit that retains the address given to the control memory in the event of an error, access delays due to usage of the memory element used in the control memory are added. By knowing this in advance, the CPU is configured to prevent the performance of the central processing unit from deteriorating or stopping.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention, in which the microprogram word 12 read from the control storage section 2 is transferred to the holding circuit 6 using a clock signal 109 which is output earlier than the holding section 3. 12, and address 1 output from address 1 with the same clock signal 109.
1 is set in the address holding circuit 8.

An output address 21 of the address holding circuit 8 is connected to the logic section 6. The microprogram word 22, which is the output of the holding circuit 99, is sent to the check circuit 10.
An ECC check is performed.

The check circuit 10 sets the error signal 108 to a logic value "0" if the check results in an error, and outputs a logic value "1" if there is no error. error signal 1
If 08 is a logical value “0”, the clock signal 109
AND circuits 201 and 202 for taking a logical value
Since the output becomes a logic value "0" and the signal 109 output in the next step is not set in the address holding circuit 8 and the holding circuit 9, the error state is held as is.

The error signal 103 is also connected to the logic unit 6, and the logic unit 6 includes a circuit that holds information indicating that the central processing unit is currently operating normally but may malfunction over time. When the information is set in the circuit, an interrupt is sent to the firmware, and the interrupted firmware investigates the cause of the interrupt and notifies the software to issue a warning message to the operator. Therefore, when the error signal 108 has a logic value of "0", the logic section 6 sets it to that circuit, and also takes in the output address 21 as information at the same time.

If the logic section 6 has enough circuitry to incorporate the microprogram word 22, the microprogram word 2
You can also include 2.

Note that the timing of outputting the clock signal 109 may be determined according to the margin of the calculation formula that determines the timing of outputting the clock signal 104.

In the central processing unit of the present invention, by adding a holding circuit in which the read microprogram is set at an earlier timing than the holding part, the operator can access the storage element of the control storage part of the central processing unit according to the usage history. By knowing the delay in advance, maintenance parts can be replaced at an appropriate time, which has the effect of reducing the frequency of central processing unit performance deterioration or system downtime.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1...address section, 2...control storage section, 3...
Holding section, 4... Check section, 5... Selection section, 6...
...Logic part, 7...Clock part, 8...Address holding circuit, 9...Holding circuit, 10...Check circuit, 11...Address, 12...Microprogram word, 13...Microprogram word, 14...
...Microprogram word, 15...Microprogram word, 16...Address, 101...1 bit error instruction signal, 102...2 or more bit error instruction signal, 103-105...Clock signal,
106...Clock delay signal, 107...Clock stop signal, 22...Microprogram word, 1
08...Error signal, 109...Clock signal,
201, 202...AND circuit.

Claims (1)

[Scope of utility model registration request] a control memory section that stores a microprogram consisting of a microprogram word to which ECC bits are added; an address section that stores an address for reading the microprogram word from the control memory section; A holding section for holding the read microprogram word, and an ECC check of the microprogram word held in the holding section, and when there is a 1-bit error, the error bit is automatically corrected, and the 1-bit error is automatically corrected.
a check section which outputs a bit error indication signal and outputs a 2 or more bit error indication signal when there is an error of 2 bits or more; A selection section which switches the program word in response to a 1-bit error instruction signal, and a selection section which operates based on the microprogram word outputted from the selection section, further determines the next address of the microprogram, and controls the clock section based on the error signal from the check section. against 1
A logic section that outputs a clock delay signal that instructs to delay the output timing of the supplied clock signal in the case of a bit error, and outputs a clock stop signal that instructs to stop the clock in the case of an error of 2 or more bits; a clock unit that supplies a clock signal to the holding unit and the logic unit; a holding circuit that holds a microprogram word read out at a timing earlier than the timing at which the holding unit holds the word; A check circuit that performs an ECC check on a microprogram word and sends an error signal to the logic section when the check results in an error; and an address holding circuit that holds the address when the error signal is supplied. A central processing unit characterized by: