JPS63221444A - Control memory device - Google Patents

Abstract

PURPOSE:To ensure the suitable control correction by reading an error correction code to a correction circuit when a parity error of a control instruction is detected, deciding the propriety for correction of said correction code as well as the control instruction containing the parity error and producing the correction data if the parity error is correctable. CONSTITUTION:A control instruction parity error detecting circuit 7 detects a parity error when a parity check bit 4 and a control instruction 3 stored in a control memory 1 are read out to a control instruction register 6. In this case, the circuit 7 outputs a correcting action start instruction to a correction circuit 8. The circuit 8 reads an error correction code out of an external mem ory 2. Then the circuit 8 decides the propriety for correction between the error correction code and the control instruction of the register 6. If the correction is possible, the correction data is produced and stored into a correction data storing register 9. Thus, a parity error is corrected when the control instruction is read out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a system that reads control instructions from a control storage device and operates according to the instructions. Regarding the method.

[Conventional technology]

This is a correction method when a control command is read from the control storage device and there is an error in the control command.

A correction method that has vertical parity check bits (sum check data) in the control storage device and creates correction data using the vertical parity check bits, and a backup of control instructions with the same content as the control storage device in the external storage device. There is a correction method in which the control command is read out again from an external storage device when an error is detected.

[Problem that the invention seeks to solve]

The above-mentioned prior art has a vertical parity check bit (Samchetaf data) of a control instruction in a control storage device and detects it using a horizontal parity check bit. Since correction data is created using vertical parity check bits corresponding to each bit of a control instruction in which a parity error has occurred, if the bit width of the control instruction becomes long, the correction operation takes time.

Furthermore, the method of reading out multiple control instructions from the external storage device again using a backup of control instructions prepared in the external storage device increases the amount of hardware or data of the external storage device.

Additionally, an error correction code (EC) is added to the control instructions in the control storage device.
There is also a method that detects and corrects errors by adding C), but since it is necessary to control the error υ correction code when reading the control command, the hardware becomes complicated and the execution time for one control command increases. There was a problem.

An object of the present invention is to eliminate the above-mentioned problems and to realize a highly reliable and inexpensive computer system. The object of the present invention is to provide a correction method for a control storage device.

[Means for solving problems]

A control storage device that stores control instructions and parity bits, a control instruction register that reads and stores control instructions and parity check bits, a control instruction parity error detection circuit, and, when a parity error is detected, an error correction device stored in the external storage device. It is constituted by a correction circuit that determines whether or not correction is possible based on the code and a control command stored in a control command register, and if correction is possible, creates correction data and stores it in a correction data storage register. By providing the above configuration, the above object is achieved.

[Effect]

When the control instruction and parity check bit 4 stored in the control storage device are read into the control instruction register, if a parity error is detected by the control instruction parity error detection circuit, the parity error detection circuit is activated by the correction circuit. Instructs to start corrective action.

1. The positive circuit reads out the error correction code from the external storage device. The correction circuit determines whether correction is possible between the control command in the control command register and the error correction code, and if correction is possible, creates correction data. Store in the correction data storage register.

According to the above, errors at the time of reading the control command can be relieved.

〔Example〕

An embodiment of the first aspect of the present invention will be described below with reference to FIG.

FIG. 2 is a diagram showing a configuration example of the present invention. The control memory 1 is connected to a control instruction register 6 which reads and stores the control instruction 3 addressed by the address register 10 and the control instruction parity check bit 4.

The external storage device 2 is connected to a correction circuit 8&C which reads out the error correction code 5 for the control command addressed by the address register 11.

The correction circuit 8 is connected from the external storage device 2 to the error correction code 5 and the control command register 6.

The control commands are read out in order by the control storage device address register 10 and stored in the control command register 6 to control the system.

When the control instruction 3 and parity check bit 4 are stored in the control instruction register 6, a parity error detection circuit 7 detects a parity error in order to confirm that the control instruction 3 is correctly stored in the control instruction register 6. To check. At this time, if the parity error detection circuit 7 detects a parity error υ, the operation of the control storage device 1 is stopped. The parity error detection circuit 7 issues an instruction to the correction circuit 8 to start a correction operation.

The correction circuit 8 converts the external storage address register 11 of the external storage device 2 into an address that corresponds to the control storage device address register 10, and outputs the error υ correction code 5 for the control instruction in which the parity error υ has occurred to the external storage device. 2 yo υ read out,
Using the error correction code 5 and the data in the control instruction register 6, it is determined whether correction is possible, and if correction is possible, the control instruction is corrected and stored in the correction data storage register 9.

Next, the correction circuit 8 transfers the contents of the correction data storage register 9 to the control command register 6 and restarts the control storage device 1. The control command register 6 resumes system operation according to the control command stored by the correction circuit 8.

According to this embodiment, when a control command is read out, it is only necessary to control the error correction code when a parity error in the control command occurs, and since the error correction code is not required in the shave control device, This has the effect of suppressing the increase in instruction execution time due to error correction code control of the control storage device and minimizing the bit width of the control instruction including the error check bit of the control storage device.

〔Effect of the invention〕

According to the present invention, there is a first-order effect.

(11) If a parity error occurs when reading a control instruction, the control instruction can be corrected, so a highly reliable computer system can be realized.

(2) By eliminating the error correction code check processing time when reading a control instruction, the execution time for one control instruction can be shortened.

(3) By storing error correction codes in an external storage device other than the control storage device, the bit width of control instructions in the control storage device can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a correction method in a control storage device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a correction method in a control storage device according to an embodiment of the present invention. 1... Control storage device, 2... External storage device, 3...
- Control instruction group, 4... Parity check bit, 5...
Error correction code, 6... Control instruction register, 7... Parity error detection circuit, 8... Correction circuit, 9... Correction data storage register, 10... Control storage device address register, 11. ...External storage device address register.

Claims (1)

[Scope of Claims] 1. A means for reading and storing a control instruction and a parity check bit in a control storage device in a system that reads a control instruction from a control device storing a control program and operates according to the instruction; and a means for detecting a parity error when reading a parity check bit, a means for reading an error correction code (ECC) in an external storage device, and a means for determining whether correction is possible based on a control command and an error correction code when detecting a parity error, If correction is possible, the correction position,
In a device equipped with a correction circuit that creates correction data, if a parity error in the control instruction is detected when reading the control instruction and parity check bit in the control storage device, a parity error stored in the external storage device will occur. The error correction code corresponding to the control command is read out to the correction circuit,
A control storage device characterized in that a correction circuit determines whether or not correction is possible based on a control command that detects a parity error, and if correction is possible, creates correction data.