JPS63221444A - Control memory device - Google Patents

Control memory device

Info

Publication number
JPS63221444A
JPS63221444A JP62054059A JP5405987A JPS63221444A JP S63221444 A JPS63221444 A JP S63221444A JP 62054059 A JP62054059 A JP 62054059A JP 5405987 A JP5405987 A JP 5405987A JP S63221444 A JPS63221444 A JP S63221444A
Authority
JP
Japan
Prior art keywords
correction
control instruction
circuit
error
parity error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62054059A
Other languages
Japanese (ja)
Inventor
Akira Noda
Kazunobu Mimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Computer Electronics Co Ltd
Hitachi Ltd
Original Assignee
Hitachi Computer Electronics Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Computer Electronics Co Ltd, Hitachi Ltd filed Critical Hitachi Computer Electronics Co Ltd
Priority to JP62054059A priority Critical patent/JPS63221444A/en
Publication of JPS63221444A publication Critical patent/JPS63221444A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To ensure the suitable control correction by reading an error correction code to a correction circuit when a parity error of a control instruction is detected, deciding the propriety for correction of said correction code as well as the control instruction containing the parity error and producing the correction data if the parity error is correctable.
CONSTITUTION: A control instruction parity error detecting circuit 7 detects a parity error when a parity check bit 4 and a control instruction 3 stored in a control memory 1 are read out to a control instruction register 6. In this case, the circuit 7 outputs a correcting action start instruction to a correction circuit 8. The circuit 8 reads an error correction code out of an external mem ory 2. Then the circuit 8 decides the propriety for correction between the error correction code and the control instruction of the register 6. If the correction is possible, the correction data is produced and stored into a correction data storing register 9. Thus, a parity error is corrected when the control instruction is read out.
COPYRIGHT: (C)1988,JPO&Japio
JP62054059A 1987-03-11 1987-03-11 Control memory device Pending JPS63221444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62054059A JPS63221444A (en) 1987-03-11 1987-03-11 Control memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62054059A JPS63221444A (en) 1987-03-11 1987-03-11 Control memory device

Publications (1)

Publication Number Publication Date
JPS63221444A true JPS63221444A (en) 1988-09-14

Family

ID=12960042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62054059A Pending JPS63221444A (en) 1987-03-11 1987-03-11 Control memory device

Country Status (1)

Country Link
JP (1) JPS63221444A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04117529A (en) * 1990-09-07 1992-04-17 Koufu Nippon Denki Kk Microprogram controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04117529A (en) * 1990-09-07 1992-04-17 Koufu Nippon Denki Kk Microprogram controller

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