JPH045219B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] This is a memory error handling method for a memory system equipped with an ECC circuit, in which a correctable error is not immediately corrected in the memory, and the address is not written to by a predetermined timing. At the same time, by modifying the data in memory, the number of data modifications can be reduced.

[Industrial application field]

The present invention relates to a processing method when an error occurs in a memory system having a circuit (ECC circuit) for detecting and correcting memory data.

2. Description of the Related Art As semiconductors used in information processing devices become more integrated, they operate using extremely weak electrical signals.

Therefore, external noise, such as alpha rays, is also affected, and although preventive measures are taken, errors cannot be completely prevented and errors occur.

As the size of the system increases, the damage caused by failures also increases, so methods are used to automatically correct such temporary failures.

If an error occurs in the data read from memory, an error correcting code (ECC) is added in advance, and even if an error occurs, if it is one bit in the data, the added
Correct data is restored based on ECC, and if there is an error of 2 bits or more, it is detected and treated as an error failure.

However, even if an error in the read data is detected, the data corrected by ECC is sent out, and the memory data is immediately corrected, the data write occurs before the data at that address is read next. In this case, the data at that address will be rewritten, and the painstaking effort to correct the data will be wasted.

Memory is occupied while data is being modified or rewritten, so if a write or read processing request is received while data is being modified or rewritten, the write or read processing will have to wait, resulting in system processing time. It will take that long.

Therefore, there is a need for a rational method that reduces the number of corrections and writes as much as possible and shortens the data processing time as much as possible.

[Conventional technology]

FIG. 4 shows a block diagram of a memory system with a conventional ECC circuit.

When reading data stored in the memory 1, when an address is designated by a read command, the data at that address is stored in the register 2.

In a memory system equipped with ECC circuit 3,
When the ECC circuit 3 checks this data and detects a 1-bit error, the
Correct data is restored based on ECC and sent from register 2.

Meanwhile, the modified data is written to the same address in memory. That is, the data in the memory is also modified.

Further, if the ECC circuit 3 detects that an error of 2 or more bits has occurred, the ECC circuit 3 cannot automatically correct the error, and other error processing will be performed as a data error.

[Problem that the invention seeks to solve]

In a memory system in which error correction is performed using an ECC circuit, when a correctable error occurs, correction is usually performed immediately.

However, if data is written to the same address before the modified data is referenced, the previous data will be erased and replaced with new data, so the process of storing the modification will be wasted. I end up.

Therefore, there is a need for a rational error handling method that reduces the number of memory rewrites.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the memory error processing method of the present invention.

In the figure, 1 is a memory that stores data; 2 is a memory that stores data;
3 is a register that stores the data read by the read command, 3 is an ECC circuit that has the same function as the conventional one to check the data in register 2, and 4 is an ECC circuit that has the same function as the conventional one.
an error address memory 41 that stores the address of the ECC circuit 3 and the detected error data;
This is an ECC processing unit consisting of a counter 42 that counts the number of memory errors.

The contents of the error address memory 41 are stored at a predetermined timing, such as the next level change signal (when one processor has a plurality of execution levels that operate independently and perform different tasks, the transition between the levels is detected). If writing has been done to the same address in the memory by the command signal), or if no writing has occurred, it will be cleared when the level change signal is input, and if no writing has occurred, modified data will be written to that address. It will be done.

The counter 42 counts the number of addresses registered in the error address memory 41.

Also, the number of memory errors, that is, the counter 4
When the value of 2 reaches a predetermined number of times, error correction storage is performed regardless of whether or not there is writing to the same address.

[Effect]

Even if an error occurs, the data stored in the memory is not corrected immediately, but the correction is deferred until a predetermined timing, and if there is writing by then, the correction process can be omitted.

Additionally, the error data stored in the register is
Since it is corrected immediately when it is detected, the original error correction function is not impaired.
Furthermore, there is no effect on the next stage of processing.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the memory error handling method of the present invention.

FIG. 3 is a state transition diagram.

Note that the same reference numerals indicate the same objects throughout the figures.

Reference numeral 5 designates an address register for specifying the read/write address of the memory 1, which exchanges contents with the error address memory 41 of the ECC processing section 4, and is configured so that a comparison circuit 6 can compare the contents with the error address memory 41. There is.

The operation of the embodiment of the system of the present invention will be described below with reference to state transition diagrams.

Hereinafter, status steps are indicated by numbers in parentheses.

Starting from the error-free state (1), when reading is commanded to the memory 1, the read data is stored in the register 2, and the ECC circuit 3 of the ECC processing unit 4 performs an error check, and if an error is detected, it can be corrected. If it is a 1-bit error, it is corrected and the corrected data is stored in register 2.

On the other hand, store that address in the error address memory 4.
1, and ₊₁ is added to the counter 42. In other words, state (2) occurs in which a 1-bit error occurs once.

Furthermore, if a 1-bit error occurs before the next level change signal is input, a state (3) of two 1-bit errors and a state (4) of 3 or more 1-bit errors will occur.

Then, each error address is registered in the error address memory 41, and the counter 42 is incremented _by 1 each time.

During this period, if there is a write to the memory 1, the comparator circuit 6 compares the address with the registered address in the error address memory 41 each time, and if the address is a registered address, the address is cleared from the error address memory 41 and the counter 42 is decremented by 1.

That is, state (3) becomes state (2), and state (2) becomes state (1).

When a level change signal is input, states (2) to (4)
The recovery routine operates from then on, and enters state (5), in which all data in memory 1 at the address of error address memory 41 is corrected, and error address memory 41 and counter 42 are cleared.

When this operation is completed, the state becomes (1).

If a 2-bit error occurs in states (1) to (4), another uncorrectable error process (6) is performed.

If the value of the counter 42 reaches a predetermined value before the level change signal is input, the recovery routine is activated by the next level change signal.

〔Effect of the invention〕

As described above, according to the present invention, error handling in a memory system with an error correcting function is streamlined, and unnecessary correction routines no longer need to be executed, which is extremely useful in practice. .

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the error processing method of the memory system of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a state transition diagram, and Fig. 4 is a block diagram of a conventional example. be. In the figure, 1 is memory, 2 is register, and 3 is
4 is an ECC processing unit, 41 is an error address memory, and 42 is a counter.

Claims (1)

[Claims] 1: A memory 1 that stores data, a register 2 that stores data read from the memory 1, and an error correcting circuit (ECC circuit) 3 that detects and corrects errors in the data. In the memory system, an error address memory 41 for storing an address in which a correctable error has occurred, and a counter 42 for counting the number of correctable errors in the memory 1 are attached to the ECC circuit 3, When an address is written, the address in the error address memory 41 is cleared, and the count value of the counter 42 is subtracted by a certain number, and when the count value of the counter 42 exceeds a predetermined value, , a memory error handling method characterized in that data at the address is corrected and rewritten.