JPH0520213A - Storage device - Google Patents

Abstract

PURPOSE:To prevent the generation of an error even when a bit fault occurs on the halfway of reading out data from a memory circuit. CONSTITUTION:When an ECC circuit 4 detects/corrects the error in data read out from the memory circuit 1, a microprocessor 5 sets up an 1/n selective flag register 7. Based upon the operation, the corrected data of a bit error position judged by the ECC circuit 4 are written in a redundant bit memory circuit 2. The operation is repeated until the end of data reading from the memory circuit 1. After completing the data reading, a 1/2 switching circuit 3 is started, the data of a fixed failure bit position are switched and correct data are outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device, and more particularly to a storage device using a semiconductor memory for a disk cache and a semiconductor storage device for a semiconductor disk cache.

[0002]

2. Description of the Related Art Conventional data does not include address parity. Further, since the data of the fixed bit position of the bit is switched only at the time of start-up, there is a drawback that a fixed bit failure during running causes a serious accident in the system.

[0003]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a storage device capable of preventing the occurrence of an error even if a bit failure occurs during running.

[0004]

A storage device of the present invention switches a memory circuit for storing data and an additional bit for ECC and a redundant bit respectively, data at a bit position of a fixed failure, and data from a redundant bit. ½ switching circuit, a microprocessor that transfers the bit position at the time of a 1-bit data error detected by the ECC circuit to the ½ selection flag register and the 1 / n selection flag register, and a 1-bit data error A 1 / n switching circuit for designating the data of the bit position at the time, the ECC circuit receives the data read from the memory circuit, confirms the position if a certain bit is defective, and corrects the data. , The data of the fixed fixed bit position after correction is stored in the redundant bit, and is switched by the 1/2 switching circuit while running. Characterized in that to the output as data.

[0005]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a storage device. This storage device includes a memory circuit 1 for storing data and ECC check bits, a memory circuit 2 for storing redundant bits, a read data line 101 of the memory circuit 1, and a read data line 105 of the memory circuit 2. Connected to each of them, the bit failure position of the data on the data line 101 can be replaced with the data on the data line 105.
E receiving the data on the data line 102 after switching which is the output of the 2 switching circuit 3 and the 1/2 switching circuit 3 to detect and correct the memory error and detect the error bit position E
A CC circuit 4, a data line 103 that outputs data including a syndrome indicating an error bit position detected by the ECC circuit 4, a microprocessor 5 that receives data on the data line 103, and determines an error bit position; 1 / n switching circuit 8 for receiving data on line 103
, 1/2 selection flag register 107, 1 / n selection flag register 108, and the error bit position signal determined by the microprocessor 5 to the 1/2 selection flag register 6
And an error bit position signal 106 transferred to the 1 / n flag register 7 and a data line 107 transferred from the 1/2 selection flag register 6 to the 1/2 switching circuit 6, respectively.
1 / n selection flag register 8 to 1 / n switching circuit 4
And the data line 104 for transferring the data at the bit position of the fixed fault from the data on the data line 103 from the ECC circuit 4 by the signal line 108 from the 1 / n selection flag register 7. Have

When data is read from the memory circuit 1 in the storage device having the above configuration, the data on the read signal line 101 which is the output of the memory circuit 1 is input to the 1/2 switching circuit 3. 1 at the first reading
All the signal lines 106 and 107 from the / 2 selection flag register 6 and the 1 / n selection flag register 7 are off, and the data on the corrected data line 102 has the same value as the data on the read signal line 101. Becomes When the data on the corrected data line 102 is input to the ECC circuit 4, E
The CC circuit 4 determines whether or not the data has an error, and if there is no error, the value on the corrected data line 102 is directly output to the corrected data line 103. When the data on the corrected data line 102 has a 1-bit error, the ECC circuit 4 corrects the 1-bit error and outputs the corrected data to the corrected data line 103. At this time, the ECC circuit 4 puts the corrected bit position on the data line 103 together with the data. Upon receiving the data on the data line 103, the microprocessor 5 sets the 1 / n selection flag register 7 via the signal line 106. 1 / n selection flag register 7
By setting, the data after the correction of the fixed fault bit position is written in the redundant bit.

By repeating these steps, the data in the memory circuit 1 is read from the start address. When the data has been read to the end, the 1/2 switching circuit 3 is started to switch between the data at the fixed fault bit position and the data at the redundant bit.

[0009]

As described above, the present invention stores the data of the bit position of the fixed fault in the redundant bit,
When the reading of all is completed, the data of the bit position of the fixed failure and the data of the redundant bit are switched by the 1/2 switching circuit. This has the effect of preventing the occurrence of errors.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of Codes] 1 check bit memory circuit for data and ECC 2 redundant bit memory circuit 3 1/2 switching circuit 4 ECC circuit 5 microprocessor 6 1/2 selection flag register 7 1 / n selection flag register 8 1 / n switching Circuit 101 Read data line 102 Data line after switching 103 Data line after correction 104, 105 Data line 106, 107, 108 Signal line

Claims (1)

Claim: What is claimed is: 1. A memory circuit for storing data and an additional bit for ECC and a redundant bit respectively, data at a bit position of a fixed failure, and data from the redundant bit. A switching circuit, a microprocessor that transfers the bit position at the time of 1-bit data error detected by the ECC circuit to the 1/2 selection flag register and the 1 / n selection flag register, and a bit position at the time of 1-bit data error A 1 / n switching circuit for designating data, the ECC circuit receives data read from the memory circuit, confirms a position if a certain bit is defective, corrects the data, and fixes the corrected data. The data at the faulty bit position is stored in the redundant bit, and is switched by the 1/2 switching circuit while running to obtain the data. Storage device for causing the force.