JPS58138195A - Remote monitoring and controlling device - Google Patents

Abstract

PURPOSE:To prevent fetching of fault information when transmission and reception are performed by consisting one information with plural words, by performing checking on the continuity of the word address of the plural words and monitoring on the receiving timer of the word to be received next. CONSTITUTION:A receiving word W4 (1)2 is set in B REG 8 and a data ready signal 32 is outputted. A word address signal 33 is outputted as W4 (1) address signal 34 and set in an FF15, and, at the same time, the signal 33 triggers one- shot OSs 13 and 14 and performs receiving time out detection of a W5 (2) word. On the other hand, receiving data 35 is set in 1 buffer 25 as W4 (1) data. When nothing can be received from a receiving word W5 (2)3, the OS 13 outputs a receiving time out signal 38 and clears the FF15. Even if the word W5 (2)3 is received and a W5 (2) address signal 36 is outputted, the FF16 is not set by the NOT of an FF output 37. The next receiving word W6 (3) is also processed in the same way. Therefore, an output set signal 42 to an output buffer 28 is not outputted, and no fault combination of words is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a remote monitoring and control device that configures information that cannot be expressed in a one-word data format on the transmitting side into a plurality of words, and extracts the plurality of words as one piece of information on the receiving side. (hereinafter abbreviated as remote control device).

In conventional remote control devices, when transmitting and receiving information by composing one piece of information with multiple words, the receiving side retrieved the information only by checking the continuity of word addresses in the multiple words, so it could be interpreted as incorrect information. There were times when I had to take it out.

An object of the present invention is to provide a remote control device that generates more reliable information in a remote control device that transmits and receives information by configuring one piece of information with a plurality of words.

In a remote control device, when transmitting and receiving information by composing one piece of information with a plurality of words, for example, due to an abnormality in the transmission line, the first word of the plurality of words is received in the first reception cycle, and the first word of the plurality of words is received in the second reception cycle. In the case where the eye receives only the second and subsequent words of the plurality of words (that is, if the reception of the trial plurality of words is established due to a delay in the reception cycle), the continuity of the word addresses of the plurality of words is established, In some cases, one incorrect piece of information was extracted from the plurality of words. Therefore, the feature of the present invention is to prevent the extraction of erroneous information by using a combination of checking the continuity of word attributes of multiple core words and monitoring the reception timer of the word to be received next. This is what we are trying to prevent.

FIG. 1 shows a general transmission format in a remote control device (t, *, Sσ), and the transmission format for one cycle is j01 signal 1 followed by W. It is made up of data words from WB to WB.

Here, W, (1)2. Wa (2)3. 'W6 (
3) 4 is one piece of data consisting of 3 words, and W4 (1) 2 is the first word of the data.

Ws(2)a indicates the second word, W, and (3)4 indicate the third word. Problems with a remote control device that handles such data will be explained with reference to FIG. 1st
In transmission cycle 5, W, (2) becomes unreceivable after 3 due to an abnormality in the transmission line, and W, (2) of the next second transmission cycle 6 becomes unreceivable.
When reception becomes possible from 3, since the conventional method only checks C1 and the continuity of the word address, W4(1)2 in the first transmission cycle 5 and W in the second transmission cycle 6.

(2)3. We (3) Sometimes incorrect data was retrieved due to 40 combinations. In order to prevent this, the present invention provides words that should be received within a predetermined time, that is, W, (2
) 3, W, and (3) 4 receive timer monitoring timers are all newly provided, thereby making it possible to perform a more effective word continuity check.

Next, the circuit operation of the present invention will be explained with reference to the circuit configuration diagram in FIG. 3 and the operation time charts in FIGS. 4 and 5. 1 immediately received word W4(1)2. Wfi
(2)3. Wa (314 was received continuously. The stand will be explained with reference to Figs. 3 and 4. Transmission line 2
The word W,(t)2 prepared through 9 is transmitted to the demodulator (
DEM) 47, and one page column-to-parallel converter (S
/P) is input to 7. This demodulation (I number 30, series -
It is converted into a parallel signal 31 by a parallel converter (S-P) 7 and set in a buffer register (BR, EG) 8.

After this, the timing control circuit (T(,1)Y) 9 outputs cheetah ready@month 32 indicating the data establishment rate. Buffer register (131-1, E(1)
The word address signal 33 of No. 8 is sent to the address decoder (A
iDR, decoded by DEC) 10, W4 N)
As the address signal 34, an address decoder (A'DR
1) Output from EC)10.

W4 (1) address signal 34 is flip 70 knob 15
At the same time, OR gate 11, A, N
One shot (O8) 13.14 via D gate 12
Trigger 1~, Wfi(2) detects the reception timeout of the received word. On the other hand, the received word data 35 is W4
(1) Set in +1 buffer memory 25 as data.

After demodulating the next received word W, (2)3 in the same manner, 1-page column-to-parallel conversion is performed, and the buffer register (B
REG) is set to 8. Buffer register (B
The word address signal 33 of TLEG) 8 is decoded by the address decoder (A, T) RDEC) 10 and outputted from the address decoder (ADH, DEC) 10 as the Wfi (2) address signal 36. Wa(2
) The address signal 36 is a flip output port output signal 37.
AND, by the negative output of the reception timeout signal 38
It is set in the flip-flop 16 via the gate 18, and at the same time, the one shot <08>11.14 is triggered and the reception timeout of the Wa(3) received word is detected. - million received word data 35 ('II, We (
1) Set in +2 buffer memory 26 as data.

Similarly, for the next received word W6 (3), after demodulation, serial-to-parallel conversion is performed, and the buffer register (B
R, EG) is set to 8. Buffer register (B
T1. The word address signal 33 of EG)8 is decoded by the address decoder (ADH, DEC) 10 and outputted from the address decoder (ADH, DEC) 10 as a -We(3) address signal 39. Wa(3)
Address signal ~39 is the flip-flop output number 40
and the negative output of the reception timeout signal 38, which is set in the flip-flop 17 via the AND gate 19. On the other hand, the received word data 35 is set in the +3 buffer memory 27 as W, (t) data. Further, the 7 lip-flop output signal 41 is delayed by the delay circuit 21, and is outputted as an output set signal 42 for +1 buffer memory output data 43, +2 buffer memory data 44, +3 buffer memory output data 43,
Output buffer memory 2 of buffer memory output data 45
Set to 8. This buffer memory data 4
6 is the received word W, (1) 2, W, (2) 3, W, (3
) 4 word series, @1b data.

Next, after receiving the received word W4 (1) 2, line 29 becomes abnormal in the transmission line, and the next transmission cycle W5 (2) 3,
For the case where W, (3) 4 is received, Figures 3 and 5
This will be explained using figures. Word W received via transmission line
4 (1) 2 is demodulated by the compensation modulator 47, and 1 self-column -
It is input to a parallel converter (DEM) 7. This demodulated signal 3
0 is the parallel signal 3 by the multiplex-parallel converter (S-P) 7.
It is converted to 1 and set in the buffer register (13R, EG) 8. After this, the data ready signal 32 indicating data establishment is sent to the timing control circuit ('R,T)Y.
)9. Buffer register (B REG
)8 word address signal 33, the address decoder (
ADRDE(')10 decodes W, (t
) Address levers 1-(A, D
R,DEC)10Jtla'17]Sfl. W.

(1) The address signal 34 is input to the flip-flop 15 and at the same time passes through the OR gate 11%A and the ND gate 12 to one-shot l-13.

14 is triggered 17 to detect the reception timeout of the Wa(2) word. On the other hand, received word data 35i'z,w
, (t) are set in the +1 buffer memory 25 as data. Next, when an abnormality occurs in the transmission line according to the received word WB(2) 3, the one-shot (O8) 13 outputs the reception timeout signal 38 and clears the flip-flop 15.

Then the received word W of the next transmission cycle.

(2) If reception is possible from 3, the received word W, (
2) 3 is subjected to serial-to-parallel conversion after conversion to v4, and is set in the buffer register (B11.EG) 8. The word address signal 33 of the buffer register (B
)10, and W.

(2) An address decoder (AD) is used as the address signal 36.
RDEC) 10. However, this Wll(
2) The address signal 36 is not set in the flip-flop 70 block 16 due to the negative output of the flip-flop 11 output signal 37.

Similarly, for the next received word W6 (3), after demodulation, serial-to-parallel conversion is performed, and the buffer register (B RE
G) Set to 8. Buffer register (BR, EG
)8 word address signal 33 is sent to the address decoder (
ADH, DEC) 10 decodes Wl(3)
An address decoder (ADRDE) is used as the address signal 39.
C) Output from 10. However, this We(3) address lever number 39 is not set in the flip 70 knob 17 due to the flip output knob output signal 40. Therefore, the output set signal 42, which is the data set signal to the output buffer 28, is not output, and the output buffer 728 is not updated. On the other hand, due to reception timeout 38,
Flip-flops 15-17 are cleared.

As described above, according to the present invention, by checking the continuity of each received word address of one data consisting of a plurality of words and monitoring the reception of the next data word to be received, it is possible to prevent errors due to abnormalities in the transmission line, etc. This has the effect of not outputting song data if an incorrect combination of multiple words occurs.

[Brief explanation of the drawing]

FIG. 1 shows a general transmission format in a remote control device, FIG. 2 shows received data in the first and second transmission cycles when a transmission line abnormality occurs, and FIG.
FIG. 4 is a circuit configuration diagram of an embodiment of the present invention, and FIG. 4 is a time chart during normal reception according to the present invention, and FIG. 5 is a time chart during abnormal reception according to the present invention. 1... Synchronization signal, 2... Received word W4 (1) (3
(first word of word configuration data), 3... Received word W6 (2) (second word of three word configuration data), 4.
...Received word Wa(3) (3rd of 3 word composition data)
word), 5...first transmission cycle, 6...second transmission cycle, 7...meat tally parallel converter, 8-way buffer register, 9...timing control circuit, 1
0...Address coheader, 13-14...One shot, 15-17...Flip-flop, 21...Delay circuit, 25-27...+1-3 buffer memory,
28... Output buffer memory, 38... Reception timeout deviation, 42... Output set signal, 47... Return potato I item $2 item 7 234

Claims (1)

[Claims] 1. In a remote monitoring and control device that transmits and receives information by configuring one piece of information in a word structure, it is important to check the continuity of the word address in the word and whether the word to be subsequently received is received within a predetermined time. A remote monitoring and control device that checks whether the two check conditions are good and extracts the information made up of the plurality of words as one piece of information only when these two check conditions are good.