TW452698B - Serial communication method for data - Google Patents

Abstract

The present invention relates to a serial communication method for data that can automatically selects any two unidirectional transmission signal lines in a transmission medium (such as serial port and parallel port) as the data transmission channels. A pair of available signal lines are first selected from the current transmission medium, by means of serial transmission, before data transmission and reception can be carried out. Then, not only data transmission will not be constrained by the hardware communication protocol standards of the transmission medium but also operation will not be affected even when some transmission signal lines are defected.

Description

45269 8 _ Case No. 87117654_ Year Cr π: V. Description of the invention (1) [Scope of application of the invention] The present invention relates to a method of data communication, especially a method that is not limited by hardware. ' In any hardware protocol communication environment, it can automatically determine any two signal lines to achieve data transmission. 0 [Background of the Invention] Currently, most serial communication uses standards such as RS-232 / 422. Data must be transmitted and received through hardware that conforms to the protocol standard. Rfrj can be received in the serial or parallel port of the port for data transmission) and cannot be used online. In addition, it can only be used as a standard online. Can't find out the current hardware communication port of the invention. For example, "Serial collection" of any of the third data is incorrect. Use another letter to perform parallel testing. The structure of the problem of the abnormal signal solution is corresponding, and each of the COM signal lines is only used for signal line failures, and even the entire data line replaces the original function. At the time of the test, if the omission or line that is not available in the current test causes the second data to fail, the unexpected communication signal line is located parallel to the port to know that 4b is transmitted t 〇 The users of the test data can not fail, and Yi only has a signal line to send. Therefore, the communication line on the port is also designed to be very convenient. The theory is that the string is only used to send once (interrupt, function. The normal improperness of the multi-signal protocol, so 'the current signals that can be transmitted in both directions' can only be applied to the established standard of serial data transmission protocols , Supports communication mode that requires wires and matching hardware connection structure, and advances with a fixed hardware connection relationship.

4526㈣ Case number 87117654 V. Description of the invention (2)

In the absence of universality and transmission of information, it is impossible to transfer information normally. Automatically screen out the unsent transmission and reception by using signal lines. Drum activity, when the signal line is damaged, it is even more impossible to signal by using multiple signal lines that can cause damage. [Summary of the Invention] The main purpose of the present invention is to provide a hardware that does not require exclusive architecture. In the existing communication hardware architecture, the short-circuit and open-circuit signal lines are not used automatically. Only two unidirectional signal lines are used, and data transmission is still not carried out due to the connection relationship of the existing communication hardware architecture. A data communication method. According to the technology disclosed in the present invention, when all the output lines are placed at high and low potentials, the potential state of the input signal line is doubled and logically ORed. ) 'S calculation method, screen out the available paired signal lines, and discard the signal line pairs where the output signal line and the input signal line are short-circuited to ensure that the input of the data is not disturbed by the output of the data. When performing lean serial transmission / reception, the data bytes to be transmitted are packaged into a data packet, and the data packet is sent from the transmitting end via the output signal line. At the same time, a synchronization pulse is generated at the receiving end to detect The data packet during transmission is correct, and the check bit in the data packet is used to check whether the content of the received data packet is compatible with the data sent by the sender; therefore, even the traditional communication hardware architecture (Such as: serial port, parallel Jfu) line k is damaged to only two is normal, through the above method can also completely send data from the sender to the receiver. The detailed content and technology of the present invention are described with reference to the drawings such as

Page 5 45269 8 _Case No. 87117654_ Year and month amendment_ V. Description of the invention (3) Next: [Detailed description of the invention] As shown in "Figure 1", the communication hardware architecture disclosed by the present invention ' It includes: a sending end 1 0 having a first communication port 1 01; and a receiving end 1 1 having a second communication port 1 11 1; and a communication bus 12 having nine signal lines 12, As a communication path between the transmitting end 10 and the receiving end 11; one end of the communication bus 12 is connected to the first communication port 101, and the other end is connected to the second communication port 1 1 1; The first, third, fourth and seventh signal lines (1 21, 123, 124, 127) in the bus 12 are output signal lines for transmitting data from the transmitting end 10 to the receiving end 1; the second, sixth The eighth and ninth signal lines (1 2 2, 1 2 6, 1, 2 8, 1 2 9) are input signal lines for the transmitting end 10 to receive data from the receiving end 11; the fifth signal line 1 2 5 is the common ground line (ie, potential reference line) of each of the aforementioned signal lines.

Page 6 45269 8 _Case No. 87117654_Year_Month_Revision_ V. Description of the Invention (4) [Example 1] The test steps of the signal line function are to enable the receiving end 1 to 1 to completely receive the transmission from the sending end Before transmitting data, the present invention must first perform a performance test on each signal line in the communication bus 12 to find a usable one-way signal with normal working performance in the communication bus 12 Please refer to "Figure 2" for the signal line test flow chart of the present invention. The test steps are as follows: Step 1 A: Enter the signal line test mode; Step 1 B: All the outputs in the communication port used first The signal lines (121, 123, 124, 127) are placed at the quotient potential; Step 1C: Read the current state of the input signal lines (122, 126, 1 2 8, 1 2 9) and record them in the register A (Not shown in the figure); Step 1 D: Set the output signal lines (1 2 1, 1 2 3, 1 24, 127) to low potential again; Step 1 E: Read the current input signal line (1 2 2, 1 2 6, 1 2 8, 1 2 9), and record them in register B (not shown in the figure) Step 1F: Compare the results of reading the input signal line (1 2 2, 1 2 6, 1, 28, 129) two times before and after reading in register A and register B, and read from the same one by one The state result of the input signal line is calculated by logical OR (OR). If the calculated result is high potential (H igh), then this input signal is indicated.

The number line is short-circuited with the round-out signal line. After the short-circuited round-in signal line is calculated with 2 [it will be sent and not used; pull out k to break the line and go to short. Step 1 G: End the signal line test.

. The above logical OR algorithm, where 〇R inclusive OR, is a kind of-push private $ site slave also known as the fixed-carry system logic 遝 | ^ ^ There is a temporary difference, the result is First, whether or not t is a child, when the two operands are both zero (False), the result of the selection is zero. It is only the present invention that uses this kind of logical operation to detect any two = results, it will be zero ^ short circuit? In the process of the test of the present invention, whether the ^ lines are k lines (including an output signal) There is one line and one pair. For any-pairs, they will only change the logic. Signal line sent from the output signal line. The test process will send out the logic potential signal twice. The signal (in a logic 彳 S number h 1 gh , Another time for low-potential logic operation-artificially high potential adds any logic potential signal to the input signal line ^ | 〇w), but will not therefore, under normal circumstances without short circuit; The secondary logic potential signals will not be self-reporting signals (because there is no short circuit with each other), so the two rounds = the signal line. The potential signals should be the same without any changed logic. "(1 " Π η IV ,, ′ T, L and Θ are extended by two. The logic potential signal of the human turn is the logical result of OR (that is, the low potential Low). The corresponding value of the signal is as follows: 9 A "Conversely, when any pair of signal lines short-circuited with each other, Line two logic level signal sent are passed to the wheel & due to short circuit to each other) 'since it is twice the input logic signal lines obtained

45269 8 _Case No. 87117654_ Year and month revision_ V. Description of the invention (6) Bit signals will be different and are " Γ (high) and "(Γ (low), these two times are taken from the input signal line The result of OR logic operation on the logic potential signal is 11 Γ ′ (that is, high potential H igh). The corresponding value of the signal is shown in “Figure 9 B”. For the convenience of the following description, it is assumed that the above test is passed. Thereafter, the first signal line 1 2 1 and the second signal line 1 2 2 are normal signal lines, and in the following description, the first signal line 1 2 1 is referred to as an output signal line, and the second signal line 1 2 2 It is called an input signal line. Please also refer to "Figure 3", which is a structural diagram of a data packet used for serial transmission in the present invention, which consists of a start bit 1 3 1 and a data bit 1 3 2 And a check bit 1 3 3 to form a data packet 1 3, where the start bit 1 3 1 is a low potential, the data bit group also contains eight data bits DO to D7, and the check bit 1 3 3 is the check method that can adopt odd parity or even parity. When transmitting, it starts from the start bit 1 3 1 and then transmits the data. The least significant bit (LSB) of each element is transmitted from the sending end to the receiving end of each bit of the data packet one by one. [Embodiment 2] The step "Figure 4" of sending a data packet is shown in the present invention. Flow chart of sending data packet 1 3, the steps for sending data packet 1 3 from sender 10 are sequentially step 2 A '· ready to send data packet 1 3; step 2 B: check all signal lines, which The method is shown in "Figure 2", and find the available input signal lines and output signal lines;

4 52 69 8 _Case No. 87117654_ Year and month amendment_ V. Description of the invention (7) Step 2 C: The sender 1 〇 wait for the input signal line to be a low potential for two time periods to make the sender 1 〇 Knowing that the receiving end 1 1 is ready, you can open the data packet 13; Step 2 D: Send the start bit 1 3 1 of the data packet 1 3 to be transmitted; Step 2 E: Check the start bit 1 3 1 Whether the transmission was successful (Note 1), if it is 2F, if not, go back to step 2C; Step 2F: prepare to start sending data bytes 1 2 from the data bit DO; step 2 G: send the current Data bit; Step 2 Η: Check whether the currently sent data bit is successfully transmitted (Note 1), if it is 2I, if not, go back to Step 2C; Step 2I: Determine whether all the data bits have been sent Data bit, if it is 2 J, if not, go back to step 2 G; Step 2J: Send check bit 133; Step 2K: Check whether the check bit 1 3 3 is sent successfully (Note 1), if it is If yes, execute 2 L. If not, go back to step 2 C; Step 2 L: End the sending of the data packet. Note 1: The way to check whether sending (or receiving) is successful is according to the method shown in "Figure 6", as shown in the figure, whether it is in the output signal

Page 4 52 69 8 _Case No. 87117654_Year Month Day__ V. Description of the invention (8) Line 1 2 1 (used to transmit the data packet of the sender 10), or input signal line 1 2 2 ( It is used to transmit the information transmitted on the synchronization pulse 14 sent by the receiving end 11, and the normal data signal in each time period will have two potential states, one is high potential and the other is low potential, for example : At time period 10, the data signal on the output signal line 1 2 1 is high potential-low potential, and the data signal on the input signal line 1 2 2 is high potential-low potential, which indicates the transmitted data signal Π 1 M in hexadecimal: again, when the data signal on the output signal line 1 2 1 changes to low potential-high potential, the synchronization pulse 14 on the input signal line 1 2 2 changes to high potential-low Potential, it means that the transmitted data signal is hexadecimal " 0 " (such as the time period t 1 in "Figure 6"), but if the data signal on the signal line 1 2 1 is output during the interval If both are low or high, it means that the data sent (or received) is wrong (such as The time period t 2 and the time period t 3 in the "6th frame". [Embodiment 3] The step "Figure 5" of receiving a data packet is a flowchart of receiving a data packet 13 according to the present invention. The steps for receiving data packet 1 3 at the receiving end 11 are as follows: Step 3 A : Ready to receive data packet 1 3; Step 3 B: Check all signal lines, the method is as shown in "Figure 2", and find available input signal lines and output signal lines; Step 3 C: sender 1 0 Wait for the output signal line to be at a low potential for two time periods, so that the receiving end 1 1 knows that the transmitting end 10 is ready to receive data packets.

Page 11 ^ 52638 _Case No. 87117654_ Year and month amendment_ V. Description of the invention (9) Packet 1 3; Step 3 D: Receive the data packet 1 3 starting bit 1 3 1; Step 3 E: Check whether the reception of the start bit 1 3 1 is successful (Note 1), if it is 3 F, if not, go back to step 3 C; Step 3 F: prepare to start receiving data bits from the data bit DO Group 1 3 2; Step 3 G: Receive the current data bit; Step 3 Η: Check whether the current data bit is successfully received (Note 1), if yes, go to 31, if not, go back to step 3 C; Step 3 I: Determine whether all data bits have been received. If yes, execute 3 J, if not, go back to Step 3 G; Step 3 J: Receive check bits 1 3 3; Step 3 Κ: Check whether the reception of check bits 1 3 3 is successful. If yes, execute 3 L. If not, go back to step 3 C; Step 3 L: Check whether the check bits 1 3 3 are correct (Note 1).

-If yes, execute 3M, if not, go back to Step 3 C > Step 3M: End the reception of the data packet. Please refer to "Figure 7", which is a diagram of a normal embodiment of sending data according to the present invention. The data packet 13 includes data bytes in hexadecimal M 8 7 " Signal line 1 2 1 and input signal line 1

Page 12 45269 0 _Case No. 87117654_ year and month amendment_ V. Description of the invention (10) 2 2 At the time period t 〇, t 1 there are low potentials for two time periods at the same time, and then by the sending end 1 〇 and The receiver 11 sends data packet 1 3 and the synchronization pulse at the same time. When the receiver receives the check bit 1 3 3 from the sender and confirms that the received data packet and data byte are correct, the process ends. Data transmission; please refer to "Figure 8", which is a schematic diagram of the embodiment of the present invention when there is an error in transmitting data, a data transmission error occurred at time period t 5 'so at time periods t 6 and t 7 , Immediately make the output signal line 1 2 1 and the input signal line 1 2 2 generate a low potential for two time periods to resend the data packet 1 3. Although the present invention is disclosed in the foregoing embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some changes and decorations without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

Page 13 ^^ 2698 _Case No. 87Π7654_ Year Month Revision _ Brief Description [Schematic Illustration] Figure 1 is a schematic diagram of the communication hardware architecture of the present invention D Figure 2 is a test flow of the present invention Illustration. FIG. 3 is a schematic structural diagram of a data packet in the present invention. FIG. 4 is a flowchart of sending a data packet according to the present invention. FIG. 5 is a flowchart of receiving a data packet according to the present invention. FIG. 6 is a diagram illustrating an embodiment of judging whether the data is correct or not according to the present invention. FIG. 7 is a diagram illustrating an embodiment in which data is sent normally. FIG. 8 is a diagram of an embodiment when there is an error in sending data according to the present invention. Figure 9A, the test signal table when any pair of signal wires is normal and no short circuit occurs. Figure 9B, the test signal table when any pair of signal lines is short-circuited. [Illustration of Symbols] 10 ....... sender 1Q1 · · · · first communication port 11 receiver 1 1 1 · · · · second communication port 12 ..... communication bus 1 2 1 · · · · First signal line 1 2 2 · · * · Second signal line 1 2 3 · · · · Third signal line 1 2 4 · * · · Fourth signal line 1 2 5 · ··· Five signal lines 1 2 6 · _ · · Sixth signal line 1 2 7 · · · Seventh signal line 1 2 8 · · · · Eighth signal line 1 2 9 · * · Ninth signal line 13 .. .... data packet 131 ..... start bit 1 3 2 · * ·· data bit 133 ..... check bit 1 4 ... sync

Page 14

Claims (1)

452698 _Case No. 87117654_ Amendment Month_ (Sixth, the scope of patent application 1. A method of data serial communication, used to determine a pair of available signal lines in a communication path, in order to Data transmission between the two terminals includes: a. Finding the pair of available signal lines in the communication path by a means of inspection; and b. Two terminals of the pair of available signal lines A packet of data is transmitted between the data packets. 2 * The method of data string communication described in item 1 of the patent application, wherein the pair of available signal lines includes: an output signal line and an input signal line. 3 . The method of serial data communication as described in item 1 of the patent application, wherein the checking means can be implemented by the following steps: A · Set the output signal line of the communication path to a high potential; B. Read the communication path The state of the input signal line of the communication path; C * set the output signal line of the communication path to a low potential; D · read the state of the input signal line of the communication path; and E · compare with a logical OR algorithm Minute Read the results of the input signal line status from step B and step D to find the pair of available signal lines. 4. The method of serial data communication as described in item 1 of the patent application, where the data The packet is composed of a start bit, a data byte, and a check bit. 5. The method of data serial communication as described in item 4 of the patent application, wherein the data byte has a plurality of Bits to be sent. Page 15 ^ 5269 〇_ Case No. 8Ή17654_Year Month Amendment_ VI. Patent Application Range 6 · The method of serial communication of data as described in item 3 of the patent application, where the pair found in step E The available signal lines are those with a non-high potential after a comparison using a logical OR algorithm. 7. A method of serial data communication, in which a pair of signal lines including an input signal and an output signal is determined in a communication path in order to perform communication between two terminals located on the communication path. The steps are: a _ Set the output signal line of the communication path to a high potential; b _ Read the status of the input signal line of the communication path; c · Set the output signal line of the communication path to a low potential; d · Read the communication The state of the input signal line of the path; e. Compare the result of the state of the input signal line of the communication port from step b and step d with a logical OR algorithm to find the pair of signals Line; and f_ transmits a data packet between two terminals of the pair of signal lines. 8. The data serial communication method as described in item 7 of the patent application, wherein the data packet is composed of a start bit, a data byte, and a check bit. 9. The method of serial data communication as described in item 8 of the patent application, wherein the data byte has a plurality of bits to be sent. 10 · The method of serial data communication as described in item 7 of the patent application, wherein the pair of available signal lines found in step e are after a logical OR comparison (OR) algorithm comparison , The result is non-high potential. Page 16