JPS6125398A - Branching and inserting device of loop-like digital communication channel - Google Patents

Abstract

PURPOSE:To simplify a device and to make it to a large scale integration easily by supplying an address signal to a channel memory and providing control memory which stores the subscriber common channel relation of subscribers contained in a self station and can re-write its contents. CONSTITUTION:An intraoffice branching action executes time slot change in a channel memory 1, while in a branch line in a self station of N-number of time slots from a down loop transmission line, execute the correspondence to L-number of fixed time slots on a output channel highway 41. As a result, a line can be branched to self station subscribers through separator circuits 4 and 8. Moreover, an intraoffice inserting action means that subscriber information in a specific self station is fixedly multiplexed in an input channel highway 31 through multiplexing circuits 7 and 3, and in order to replace time slots in a memory 1 and insert them into N-number common channels to an up loop transmission line, the replaced time slots are corresponded to N-number of time slots on the highway 41. A memory 2 executes the control of such branching and insertion.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to time division multiplexed communication paths. In particular, in a loop-shaped communication path in which multiple stations are connected in a skewer shape and connected to form a loop as a whole, the subscriber communication path of each station is connected to this loop-shaped common communication path and used for common use. This invention relates to a communication channel that forms a concentrating configuration by doing so.

[Conventional technology]

Conventionally, as shown in FIG. 4, a communication network has been known in which a large number of subscribers can appropriately access a loop-shaped common communication path depending on the number of communication paths, and perform distributed line concentration within the loop. There is. The technology used here is
This is a multiplexing/demultiplexing technology using conditional branching and conditional insertion.

The main points of the cause will be explained with reference to Fig. 5. First, to explain conditional branching, the number of common communication paths is N,
Time slot numbers 1 to N in the time division multiplex arrangement are assigned to these N communication paths. The number of subscribers of a certain station is generally L, which is larger than the value of N, and subscriber numbers #1, #2-#L are assigned to each subscriber. Now, when control is performed in this station so that subscribers #1, #3, and #L can use the common channel, channel pulses are emitted to each subscriber as shown in FIG. For example, in the figure, subscriber #1 uses time slot 5, and subscriber #3 uses time slot (N-1).
, subscriber #L is assigned time slot 2. Other subscribers are not allowed to use the common channel and are not given a channel number. Each subscriber can branch out and incorporate information on the common channel only at significant times when his or her channel pulse is applied. Since other subscribers are not given this condition, they cannot branch information on this call path.

Next, to explain conditional insertion, in the same way as in the explanation of conditional branching above in FIG. and insert it into the common channel.

[Problem that the invention seeks to solve]

In this conventional multiplexing and demultiplexing technology using conditional reference drop/add, firstly, the configuration of the generation circuit and the control circuit for generating channel pulses, which have different phases for each subscriber, is complicated;
In the second subscriber circuit, the pulse position of its own communication path changes depending on the usage situation, so a circuit to operate in synchronization with this phase is required, resulting in a complex and large-scale hardware configuration. There are drawbacks to it. This is because each subscriber is assumed to operate independently, since the phase assignment is performed on a subscriber-by-subscriber basis in accordance with the channel designation. In this sense, a branch/add circuit with a simple configuration in which all subscriber operations are fixed has been desired.

The present invention provides a branching/inserting multiplexing/separating circuit that has a simple configuration, can perform economical branching/insertion, and can easily control the branching/insertion multiplexing/separating circuit, in place of the conventional conditional branching/insertion multiplexing/separating circuit described above. The purpose is to provide

[Means for solving problems]

The present invention includes a random access type communication path memory, a control memory for storing the writing and reading order of the communication path memory and inputting the information into the communication memory in an address form, and a control memory disposed on the input side of the communication path memory. a multiplexing circuit for time-division multiplexing a total of (N+L) communication paths between the receiving side of the N common communication paths of the loop-shaped communication paths provided and the communication paths corresponding to the maximum number of transmitting subscribers within the own station; , from the (N+L) time-division multiplexed signals arranged on the output side of the communication path memory to the transmitting side of the N common communication paths and the L communication paths corresponding to the own receiving subscribers, respectively. The present invention is characterized in that it is provided with a separation circuit that separates subscribers, and is configured to rewrite the correspondence relationship between subscribers absorbed in each station and the common communication path in the control memory.

[Effect]

The present invention fixes and simplifies the operability of each individual subscriber, eliminates the need for complex techniques such as phase multiplexing for each subscriber, and uses a channel memory and a control memory to control it. It can be easily controlled by just changing the address, the device can be simplified (LSI, etc.) and line concentration can be performed, and branching/insertion, multiplexing/demultiplexing can be performed simply and economically.

〔Example〕

Next, the present invention will be explained with reference to an embodiment of the apparatus shown in the accompanying drawings. 1st
The figure is a block diagram of an embodiment of the branch/add circuit of the present invention. The outputs of the control memory 2 and the multiplexing circuit are input to the communication path memory 1. The multiplex circuit circuit 3 receives N downlink transmission highways 51 connected to the transmission path input terminal 5, and outputs from the subscriber multiplexing circuit 7 to which L subscribers input are input to the L uplink connections. 71 via the public highway 71. The output of the channel memory 1 is input to the separation circuit 4 via the output channel highway 41. The N outputs of the separation circuit 4 are connected to the output terminal 6 via the uplink transmission line highway 61, and the L outputs are connected to the subscriber separation circuit 8 via the downlink subscriber highway 81. . The random access type communication path memory 1 is also a widely known time division switch. Reference numeral 2 is a control memory that stores the read and write order in the form of an address as a phase with respect to the communication path memory l.

The multiplex circuit 3 is placed on the input side of the communication path memory 1, and connects the downstream transmission line highway 51 of the multiplex arrangement having N communication paths from the input terminal 5 of the loop-shaped communication path, and the maximum number of local stations. Uplink subscriber highway 7 that multiplexes subscriber transmission information
This is a multiplexing circuit that multiplexes 1 and 1. On the other hand, the separation circuit 4 is placed on the output side of the communication path memory 1, and connects the uplink transmission line highway 61 with the newly inserted N communication paths and the maximum number of communication paths toward the output terminal 6 of the loop-shaped communication path. Downlink subscriber highway 81 on which the received information of local subscribers is multiplexed.
This is a circuit that separates the The multiplexing circuit 7 is a subscriber multiplexing circuit that constantly multiplexes the transmission information of the maximum number of subscribers and sends it to the multiplexing circuit 3 as an uplink subscriber highway 71.
On the other hand, the subscriber separation circuit 8 is a circuit that separates signals for each individual subscriber from the downstream subscriber highway 81 of the maximum number of local subscribers.

Next, the basic operation of the present invention will be explained. N time-divided common channel signals from the loop-shaped transmission channel are inputted to the down transmission channel highway 51 from the terminal 5. From this input signal, an uplink subscriber highway 71 is obtained through a multiplexing circuit 7 that operates with a synchronized clock required within the own station and fixedly multiplexes L subscriber information within the own station. These downlink transmission line highway 51 and uplink subscriber highway 71 are synchronized and further multiplexed into one input communication line highway 31 in a fixed manner. The number of communication paths at this time is (N+L) time slots. This highway is input into the communication path memory 1 of (N+L)X (N+L). The channel memory 1 is also a time division switch to which successive write addresses are given from the control memory 2, and by changing their order, time slots can be replaced. The control memory 2 receives and stores time slot allocation information for each subscriber of each station using a control signal included in the loop-shaped transmission path. The number of input and output highway time slots of call path memory 1 is (N0L)
The array is fixed. The output side of the communication path memory 1 is an output communication path highway 41 which, via a separation circuit 4, divides the fixedly arranged N time slots into an upstream transmission path highway 61 and a similarly fixedly arranged time slot downlink subscriber highway 81. be done. Downlink subscriber highway 81 is fixedly divided into L subscribers.

Here, the insertion within the local station is performed as follows. The time slots are exchanged in the communication path memory 1, and among the N time slots from the down-loop transmission path, for the communication path that branches within the local station, the output communication path highway 4 is used.
It is mapped into L time slots that are fixed at 1. It is therefore possible to branch out to the local subscriber via the separation circuits 4 and 8. Further, the insertion within the local station is performed as follows. Specific local subscriber information is fixedly multiplexed into the input path highway 31 through the multiplexing circuits 7 and 3, and the time slots are exchanged in the communication path memory 1, and the information is transferred to the uplink loop transmission path. N time slots of the output communication path highway 41 for insertion into N common communication paths. The control memory 2 performs the control regarding branching and insertion described above. At this time, branching/insertion corresponds to communication path memory reading and writing, but this can be realized by placing reading first and writing later.

FIG. 2 is a detailed block diagram of an embodiment of the drop/add circuit of the present invention. Component drawing codes 1 to 8.31.4
1.51.61.71, and 81 are the same as in FIG. 1 and include detailed views thereof. Reference numeral 9 in the drawing denotes a frame synchronization circuit that synchronizes the frame l within the own station from the down-loop transmission line, and 10 denotes a phase synchronization oscillation circuit that synchronizes the clock of the required frequency into the own station from the clock component included in the transmission line number. , 11 is a pulse generation circuit that generates pulses necessary for each part using the clock from 10, and 12 is a circuit that extracts local branch/add control signals from the multiplex code array 52 on the transmission line and stores counter information in the control memory 2. 13 is a downlink speed conversion circuit that converts the transmission line multiplexing code array 13 to the speed in the multiplexing process within its own station; 14 is a downlink speed converting circuit that performs the opposite operation and converts the uplink transmission line multiplexing code array 62. This is an upstream speed conversion circuit. The upstream part of the subscriber circuit is 701-70L, and the downstream part is 801-80L. The communication path memory 1 further comprises a parallel bit type path memory body 101, and an S-P conversion circuit 102 and a P-3 conversion circuit 103 that function to mutually convert input/output and serial signals. The control memory 2 further includes an address control memory 201 for reading, a counter 204 for creating addresses for writing, and an address switching circuit 20 for switching them.
2. It consists of register groups 205 and 206 that accommodate branch/insertion control information of the address control memory 201, and a control address switching circuit 203 that switches addresses for writing to and reading from the address control memory.

The operation of this embodiment is the same as that described with reference to FIG. 1, and an example of the multiplexed arrangement of each highway is shown in FIG.

The numbers in parentheses in this figure represent each signal point in Figure 2, N
-30 and L=226.

〔Effect of the invention〕

Because it has the configuration and operation described above, the drop/add circuit of the present invention can reduce the complexity of the equipment for the independent phase multiplexing process for subscribers in the conventional conditional drop/add circuit. In addition, since the multiplexing process can be realized in a fixed format, effects such as simplification of the device, ease of implementation in LSI, and use of LSI such as existing general-purpose memory are produced.

Furthermore, even if the number N of shared communication paths and the number of subscribers accommodated in each station are changed, the same communication path memory, control memory, etc.
It also has a flexible effect, such as being able to be used by simply changing the address.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. FIG. 2 is a detailed block diagram of a device according to an embodiment of the present invention. FIG. 3 is a diagram showing the signal multiplexing arrangement of each highway according to the present invention. FIG. 4 is an overview diagram of a conventional device. FIG. 5 is a time chart explaining the principle of the conventional device. 1...Call path memory, 2...Control memory, 3...
Multiplexing circuit, 4... Separation circuit, 5... Transmission line input terminal, 6... Transmission line output terminal, 7... Subscriber multiplexing circuit, 8... Subscriber separation circuit, 9. ... Frame synchronization circuit, 10 ... Phase synchronization oscillation circuit, 11 ... Pulse generation circuit, 12 ... Control data separation circuit, 13 ... Downlink speed conversion circuit, 14 ... Uplink speed conversion circuit, 31・
・・Human power communication path highway, 41 ・・Output communication path highway, 51 ・・Downward transmission path no＼way, 61 ・・
・Uplink transmission line highway, 71... Uplink subscriber highway, 81... Downlink subscriber highway, 101... Communication path memory body, 102... S-P conversion circuit, 103
. . . P-3 conversion circuit, 201 . . . Address control memory, 202 . . . Communication path address switching circuit, 203 .
・Control address switching circuit, 204... Curran outside 205
．． 206-=・Control information register, 701-TOL・・
-Uplink subscriber circuit, 801-80L...downlink subscriber circuit.

Claims (1)

[Claims] (1) A transmission path input terminal that is inserted and connected to a loop-shaped communication path that includes a plurality of N common communication paths, and a plurality of transmitting subscribers accommodated in the own station receive signals from the common communication path of this input terminal. a multiplexing circuit for multiplexing the signals of the multiplexing circuit; a separating circuit for separating the signals of a plurality of receiving subscribers accommodated in the local station from the output multiplexed signal of the multiplexing circuit; In a loop-shaped digital communication path add/drop device having a transmission path output terminal for connecting a communication path signal to the loop-shaped communication path, the output of the multiplexing circuit is connected to the write input, and the read output is connected to the above-mentioned. A random access type communication path memory is connected to the input of the separation circuit, and an address signal is supplied to this communication path memory to store the correspondence relationship between the plurality of subscribers accommodated in the local station and the common communication path. , and a control memory whose contents are set to be rewritable.