JPS6331979B2 - - Google Patents

Info

Publication number
JPS6331979B2
JPS6331979B2 JP58047368A JP4736883A JPS6331979B2 JP S6331979 B2 JPS6331979 B2 JP S6331979B2 JP 58047368 A JP58047368 A JP 58047368A JP 4736883 A JP4736883 A JP 4736883A JP S6331979 B2 JPS6331979 B2 JP S6331979B2
Authority
JP
Japan
Prior art keywords
output
order group
circuit
signals
output means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58047368A
Other languages
Japanese (ja)
Other versions
JPS59172849A (en
Inventor
Takayuki Okino
Haruo Tsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4736883A priority Critical patent/JPS59172849A/en
Publication of JPS59172849A publication Critical patent/JPS59172849A/en
Publication of JPS6331979B2 publication Critical patent/JPS6331979B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems

Description

【発明の詳細な説明】 (a) 発明の技術分野 本発明はnケの低次群の信号を高次群の信号に
多重化する多重化回路に係り、特に、擾乱の影響
をなくした多重化回路に関するものである。
[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a multiplexing circuit that multiplexes n low-order group signals into a high-order group signal, and particularly relates to a multiplexing circuit that eliminates the influence of disturbance. It is related to.

(b) 従来技術と問題点 従来の多重化回路の一実施例を図を用いて説明
する。尚、ここでは、PCM信号を多重化する場
合を例にとつて説明する。第1図は従来のPCM
伝送装置のインターフエイス部の一実施例構成図
を示す。
(b) Prior Art and Problems An example of a conventional multiplexing circuit will be described with reference to the drawings. Incidentally, here, a case where PCM signals are multiplexed will be explained as an example. Figure 1 shows conventional PCM
1 shows a configuration diagram of an embodiment of an interface section of a transmission device.

図において、1乃至5はPCM24通話路群(以
下、PCM24CHと称す)、6はインタフエース部、
7乃至11は高次群変換回路、12はクロツクパ
ルス発生器、13′は論理和回路、13はインタ
フエース回路、14はPCM120CH多重変換装置、
15は出力端子である。
In the figure, 1 to 5 are PCM24 communication path group (hereinafter referred to as PCM24CH), 6 is an interface section,
7 to 11 are high-order group conversion circuits, 12 is a clock pulse generator, 13' is an OR circuit, 13 is an interface circuit, 14 is a PCM120CH multiplex conversion device,
15 is an output terminal.

第2図は、第1図の動作を説明するための図で
ある。同図1乃至8は、それぞれ第1図の1乃至
6点の信号波形を示す。
FIG. 2 is a diagram for explaining the operation of FIG. 1. 1 to 8 show signal waveforms at points 1 to 6 in FIG. 1, respectively.

第1図において、5ケのPCM24CH1〜5の
夫々の低次群のPCM信号は高次群のPCM120CH
多重変換装置14のインタフエース部6の高次群
変換回路(パネルシート)7〜11の夫々に入力
される。また高次群変換回路のクロツクパルス発
生器12より出力される各位相の異なつたφ1
φ2,φ3,φ4,φ5のクロツクパルス(以下クロツ
クと称す)は夫々に対応した高次群変換回路7〜
11に入力され、PCM24の信号を第2図1〜
5に示した高次群の信号#1〜#5に変換する。
変換された高次群#1〜#5の信号は夫々の高次
群変換回路7〜11より出力され、インタフエー
ス回路13の論理和回路(以下ORゲートと称
す)13′にて第2図6に示す如く合成され、出
力端子15より出力される。
In Figure 1, each of the 5 PCM24CHs 1 to 5, the low-order group PCM signal, is connected to the high-order group PCM120CH.
The signal is input to each of higher-order group conversion circuits (panel sheets) 7 to 11 of the interface section 6 of the multiplex conversion device 14. In addition, the clock pulse generator 12 of the high-order group conversion circuit outputs φ 1 of different phases,
Clock pulses of φ 2 , φ 3 , φ 4 , and φ 5 (hereinafter referred to as clocks) are sent to the corresponding high-order group conversion circuits 7 to 7.
11, and the signal of PCM24 is shown in Fig. 2 1~
The signals #1 to #5 of the higher order group shown in FIG.
The converted signals of higher order groups #1 to #5 are outputted from the respective higher order group conversion circuits 7 to 11, and are processed by the OR circuit (hereinafter referred to as OR gate) 13' of the interface circuit 13 as shown in FIG. 2. The signals are synthesized and output from the output terminal 15.

しかしながら、かかる第1図に示すシステム
は、以下の欠点を生じるものである。すなわち、
上記の高次群変換回路7乃至11にはそれぞれ電
源5ボルトとアースEが接続されている。ここ
で、高次群変換回路7を例にとつて説明する。い
ま、第2図7に示すAの時点で、高次群変換回路
7のパネルシートをPCM120CH多重変換装置1
4の架に挿入(着脱でも同一効果あり)する際、
電源5ボルトとアースEの何れかが先きに接続さ
れることになる。この場合どちらかが先きに接続
されることになるため、第2図7に示す如き擾乱
7−1が発生する。この擾乱7−1はORゲート
13′に入力される。ORゲート13には他の高
次群の信号#2〜#5が入力されているため、こ
の擾乱7−1によつて第2図8に示す如く他の多
重化信号(この場合#2,#3,#4)を破損す
る欠点を生ずる。
However, the system shown in FIG. 1 has the following drawbacks. That is,
A power supply of 5 volts and a ground E are connected to each of the above-described high-order group conversion circuits 7 to 11. Here, the high-order group conversion circuit 7 will be explained as an example. Now, at point A shown in FIG.
When inserting it into the rack No. 4 (the same effect is obtained even when it is attached and detached),
Either the 5 volt power supply or the earth E will be connected first. In this case, one of them will be connected first, so that a disturbance 7-1 as shown in FIG. 2 will occur. This disturbance 7-1 is input to the OR gate 13'. Since other higher-order group signals #2 to #5 are input to the OR gate 13, this disturbance 7-1 causes other multiplexed signals (in this case #2, #3 , #4).

(c) 発明の目的 本発明は前記の欠点を解決するために、伝送装
置の使用中に高次群変換回路パネルシートを着脱
しても擾乱が発生しない多重化回路を提供するこ
とを目的とする。
(c) Object of the Invention In order to solve the above-mentioned drawbacks, it is an object of the present invention to provide a multiplexing circuit that does not cause disturbance even when a high-order group conversion circuit panel sheet is attached or detached while the transmission device is in use.

(d) 発明の構成 上記目的は本発明によれば入力する並列信号を
各々割当てられた時間間隔のみ時分割で出力する
出力手段を各々入力信号に対応して複数設け、且
つ該出力手段からの出力を結合して、多重化信号
として出力する多重化回路において、該出力手段
出力の各々を各出力手段に割当てられたものと同
じ時間間隔のみ時分割で通過させる選択手段を該
出力手段の各々に対応して複数設け、該選択手段
の夫々の出力を結合するようにしたことを特徴と
する多重化回路によつて達成される。
(d) Structure of the Invention According to the present invention, the above-mentioned object is to provide a plurality of output means for outputting input parallel signals in a time-division manner only at allocated time intervals, respectively corresponding to the input signals, and to In a multiplexing circuit that combines outputs and outputs them as a multiplexed signal, each of the output means includes a selection means for time-divisionally passing through each of the output means outputs only in the same time interval assigned to each output means. This is achieved by a multiplexing circuit characterized in that a plurality of selection means are provided corresponding to the selection means, and the outputs of the respective selection means are combined.

(e) 発明の実施例 以下第3図a,bの実施例、第4図タイムチヤ
ートに基づいて説明する。
(e) Embodiments of the invention The following description will be made based on the embodiments shown in FIGS. 3a and 3b and the time chart in FIG. 4.

第3図において1〜5,7〜12,15は第1
図と同一機能を有する同一部材を示す。
In Figure 3, 1 to 5, 7 to 12, and 15 are the first
The same parts with the same functions as in the figure are shown.

すでに第1図にて説明した如く、各PCM24CH
1〜5の夫々の信号は高次群変換回路7〜11に
て第4図1〜5の多重化信号#1〜#5に変換さ
れ、夫々の信号は伝送路〜を経て選択回路1
6に入力される。選択回路16は第3図bに示す
如きANDゲート16−1〜16−5よりなる回
路構成になつている。
As already explained in Figure 1, each PCM24CH
Each of the signals #1 to #5 is converted into the multiplexed signals #1 to #5 of FIG.
6 is input. The selection circuit 16 has a circuit configuration consisting of AND gates 16-1 to 16-5 as shown in FIG. 3b.

選択回路16のANDゲート16−1〜16−
5の夫々には高次群変換回路7〜11に使用して
いるクロツクパルス発生器12より出力されるク
ロツクφ1〜φ5が入力され、このクロツクに対応
する高次群信号を夫々のANDゲート16−1〜
16−5にて選択する。
AND gates 16-1 to 16- of selection circuit 16
The clocks φ 1 to φ 5 output from the clock pulse generator 12 used in the high-order group conversion circuits 7 to 11 are inputted to each of the gates 5 and 5 , and the high-order group signals corresponding to these clocks are sent to the respective AND gates 16-1 to 16-1.
Select at 16-5.

選択された高次群の信号の夫々の伝送路イ,
ロ,ハ,ニ,ホを経てORート13′で第4図6
に示す如く#1〜#5に多重化される。
Each transmission path a of the selected higher-order group signal,
Figure 4.
The signals are multiplexed into #1 to #5 as shown in FIG.

いま、高次群変換回路7のパネルシートを前記
同様の方法でPCM120多重変換装置に挿入すると
第4図7の7−1に示す擾乱7−1が発生する。
しかし、多重化信号#1は選択回路16のAND
ゲート16−1にてφ1の位相をもつクロツクに
て選択されて出力されるのでφ1のクロツクに同
期しない擾乱はANDゲート16−1より出力さ
れない。それ故、ANDゲート16−1〜16−
5より出力される#1〜#5の高次群信号は夫々
の伝送路イ,ロ,ハ,ニ,ホを経てORゲート1
3′にて入力される。そして第4図6に示したタ
重化信号#1〜#5は第4図8に示す如く、第4
図6と同一の多重化データとなつて出力端子15
より出力される。
Now, when the panel sheet of the high-order group conversion circuit 7 is inserted into the PCM120 multiplex conversion device in the same manner as described above, a disturbance 7-1 shown at 7-1 in FIG. 7 occurs.
However, the multiplexed signal #1 is the AND of the selection circuit 16.
Since the gate 16-1 selects and outputs a clock having a phase of φ1 , disturbances not synchronized with the clock of φ1 are not outputted from the AND gate 16-1. Therefore, AND gates 16-1 to 16-
The high-order group signals #1 to #5 outputted from
3' is input. The superimposed signals #1 to #5 shown in FIG.
The same multiplexed data as in FIG. 6 is output from the output terminal 15.
It is output from

(f) 発明の効果 本発明の多重化によればインタフエース部の高
次群変換回路のパルシートの着脱の際に発生する
擾乱をそのパネルシートに対応したANDゲート
回路によつて阻止するので複数の低次群より高次
群に変換された多重化信号には擾乱の影響を除去
できる利点を有する。
(f) Effects of the Invention According to the multiplexing of the present invention, the disturbance that occurs when attaching and detaching the PAL sheet of the high-order group conversion circuit of the interface section is blocked by the AND gate circuit corresponding to the panel sheet, so that multiple low The multiplexed signal converted from the next group to a higher order group has the advantage of being able to remove the influence of disturbance.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例のPCM伝送装置のインタフエ
ース部、第2図は第1図のタイムチヤート、第3
図a,bは本発明の実施例、第4図は第3図のタ
イムチヤートを示す。 図中、1〜5はPCM24CH、6はインタフエー
ス部、7〜11は高次群変換回路(パネルシー
ト)、12はクロツクパルス発生器、13はイン
ターフエイス回路、13′は論理和回路、16は
選択回路、14はPCM120CH多重変換装置、1
5は出力端子、16−1〜16−5はANDゲー
トを示す。
Figure 1 shows the interface section of a conventional PCM transmission device, Figure 2 shows the time chart of Figure 1, and Figure 3 shows the time chart of Figure 1.
Figures a and b show examples of the present invention, and Figure 4 shows a time chart of Figure 3. In the figure, 1 to 5 are PCM24CH, 6 is an interface section, 7 to 11 are high-order group conversion circuits (panel sheets), 12 is a clock pulse generator, 13 is an interface circuit, 13' is an OR circuit, and 16 is a selection circuit. , 14 is a PCM120CH multiplex converter, 1
5 is an output terminal, and 16-1 to 16-5 are AND gates.

Claims (1)

【特許請求の範囲】[Claims] 1 入力する並列信号を各々割当てられた時間間
隔のみ時分割で出力する出力手段を各々入力信号
に対応して複数設け、且つ該出力手段からの出力
を結合して、多重化信号として出力する多重化回
路において、該出力手段出力の各々を各出力手段
に割当てられたものと同じ時間間隔のみ時分割で
通過させる選択手段を該出力手段の各々に対応し
て複数設け、該選択手段の夫々の出力を結合する
ようにしたことを特徴とする多重化回路。
1. Multiplexing, in which a plurality of output means are provided, each corresponding to the input signal, to output parallel input signals in a time-division manner only at allocated time intervals, and the outputs from the output means are combined and output as a multiplexed signal. In the converting circuit, a plurality of selection means are provided corresponding to each of the output means for passing the output of the output means in a time division manner only at the same time interval as that assigned to each output means, and each of the selection means A multiplexing circuit characterized by combining outputs.
JP4736883A 1983-03-22 1983-03-22 Multiplexing circuit Granted JPS59172849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4736883A JPS59172849A (en) 1983-03-22 1983-03-22 Multiplexing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4736883A JPS59172849A (en) 1983-03-22 1983-03-22 Multiplexing circuit

Publications (2)

Publication Number Publication Date
JPS59172849A JPS59172849A (en) 1984-09-29
JPS6331979B2 true JPS6331979B2 (en) 1988-06-28

Family

ID=12773162

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4736883A Granted JPS59172849A (en) 1983-03-22 1983-03-22 Multiplexing circuit

Country Status (1)

Country Link
JP (1) JPS59172849A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02152336A (en) * 1988-12-05 1990-06-12 Nec Corp Digital multiplexer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5829234A (en) * 1981-08-14 1983-02-21 Matsushita Electric Works Ltd Information transmitter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5829234A (en) * 1981-08-14 1983-02-21 Matsushita Electric Works Ltd Information transmitter

Also Published As

Publication number Publication date
JPS59172849A (en) 1984-09-29

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