JP2513610B2 - Channel pulse generator - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to an improvement of a channel pulse generator used in, for example, a PCM terminal device.

[Technical Background of the Invention] In a PCM terminal device, a plurality of audio signals are digitized, multiplexed and transmitted as data D having a frame structure as shown in FIG. That is, following the synchronization signal SYNC, digitized 8-bit audio data is sequentially arranged for the number of channels (here, 24 channels). For this reason, when arranging an 8-bit audio signal on each channel or separating an 8-bit audio signal from each channel, it is necessary to arrange or separate on the corresponding time slot.

Therefore, in the PCM terminal device, as shown in FIG.
Transmit synchronization signal (STYNC), transmission clock (TCLK), reception synchronization signal (R) in PCM codec (CODEC) 1 for each channel
SYNC) and receive clock (RCLK). The PCM codec 1 starts the arrangement of the audio signal at the rising edge of the transmission synchronization signal (TSYNC) and arranges and outputs the audio signal for 8 bits of the transmission clock (TCLK). At this time, an analog audio signal is input to the PCM codec 1 from the input terminal AIN, and a digital audio signal is output from the output terminal PCMOUT. When separating the audio signal, the PCM codec 1 starts the separation of the audio signal in synchronization with the rising edge of the reception synchronization signal (RSYNC) and separates the 8-bit audio signal of the reception clock (RCLK). . At this time, PCM codec 1
A digital audio signal is input from the input terminal PCMIN of
An analog audio signal is output from the output terminal AOUT.

In this way, in the PCM terminal device, P of one channel is
It is necessary to give two channel pulses of a transmission synchronization signal (TSYNC) and a reception synchronization signal (RSYNC) to the CM codec 1. Therefore, since the number of channels is 24 in the Japan-US series PCM terminal equipment and 30 in the European PCM terminal equipment, it is necessary to give 48 and 60 channel pulses respectively. There is.

In the conventional PCM terminal equipment, all channel pulse generators are provided in a common section, and the PCM codec 1 is provided for each channel in the voice channel board. Then, the transmission of the channel pulse from the common section to each audio channel board is performed by the connector cable.

[Problems of background art] Therefore, in the conventional PCM terminal equipment, the number of pins of the connector in the common part is extremely large, such as 48 or 60, and there is a drawback that the connector becomes large. Along with this, there has been a problem that miniaturization of the PCM terminal equipment is hindered.

[Object of the Invention] The present invention has been made in order to solve the above problems, and an object of the present invention is to reduce the size of the connector of the common part and to reduce the size of the device as a whole. It is to provide a possible channel pulse generator.

SUMMARY OF THE INVENTION Therefore, in the present invention, a frame signal generating means for generating a frame signal for instructing the start of one frame including a predetermined number N of channels and a channel clock for instructing the start of each channel of the one frame are provided. A common part having a channel clock generating means for generating, and a common part connected to the common part, initialized by a frame signal generated by the frame signal generating means, and counted by a channel clock generated by the channel clock generating means. A counter that outputs a pulse at the count value of the initial value that has been set up and a pulse that is output by this counter is shifted by the channel clock generated by the channel clock generating means and sequentially output from M output terminals. Equipped with a shift register to output , In which the pulses output from the output terminals of the shift register, and a channel pulse generator to provide the PCM codec corresponding respectively one channel.

[Embodiment of the Invention] FIG. 1 is a block diagram of a main part of a PCM terminal device adopting an embodiment of the present invention. The PCM terminal device 100 is of the Japan-US series and has a data structure of one frame with 24 channels. In this embodiment, only the configuration for obtaining the transmission synchronization signal is shown. In the figure, reference numeral 3 denotes a common portion, and the common portion 3 is provided with a frame signal generating means (pulse output circuit) 31 and a channel clock generating means (pulse output circuit) 32. Frame signal generating means 31
Is a frame signal TSφ (1
Signal with a pulse at the beginning of the frame). The channel clock generating means 32 outputs a channel clock CHCLK (a signal having a pulse for every 8 bits) for instructing the start of each channel. The relationship between the frame signal TSφ and the channel clock CHCLK and the multiplexed data D is as shown in FIG. The frame signal TSφ and the channel clock CHCLK are given to the counters 6A1 to 6A24 of the channel units 2A1 to 2A24 via the signal lines 4 and 5, respectively. The counters 6A1 to 6A24 have the same configuration and are initialized when the frame signal TSφ rises to have an initial value given via the 5-bit signal lines 8A1 to 8A24, and then the channel clock CHCLK When a pulse arrives, it counts up, and when the counter value is "25", the output is H level, and when the count value is any other value, the output is L level.
The outputs of the counters 6A1 to 6A24 are given to the transmission sync signal input terminals of the PCM codecs 1A1 to 1A24 of the respective channels via the signal lines 7A1 to 7A24, respectively. The initial value of 5 bits is
Although it is supplied from a control unit (not shown), it is supplied by each of the channel units 2A1 to 2A24. And each counter 6A1 ~ 6A24
The initial value given to the counter 6A1 is 24 (1
1000), counter 6A2 has 23 (10111), ..., (Omitted),
..., 1 (00001) is given to the counter 6A24.

The operation of the channel pulse generator configured as above will be described. When a pulse of the frame signal TSφ is output from the frame signal generating means 31 of the common section 3, the counter 6A
Initialization of 1 to 6A24 sets the count value to 24 to 1, respectively. Next, when the first pulse of the channel clock CHCLK is output, the count value of the counters 6A1 to 6A24 is 25.
~ 2. Therefore, the output of the counter 6A1 becomes H level, and the outputs of the counters 6A2 to 6A24 remain L level. Then, the second value of the channel clock CHCLK is output, and the count value of the counters 6A1 to 6A24 is 26 to
It becomes 3. As a result, the output of the counter 6A2 becomes H level, and the outputs of the counters 6A1, 6A3 to 6A24 become L level. As a result, the counter 6A outputs a channel pulse (transmission synchronization signal) of H level in the section corresponding to the first 8-bit data of one frame. Below, a counter 6 is generated at each arrival of a pulse of the channel clock CHCLK
Channel pulses are output sequentially from A2 to 6A24. PCM
Each of the codecs 1A1 to 1A24 arranges audio data based on the incoming channel pulse. Since only the transmission system is shown in this figure, in actuality, the common section 3 is provided with the frame signal generation means and the channel clock generation means for the reception system, and each channel section 2A.
Each of 1 to 2A24 is provided with a counter for generating a reception synchronization signal (RSYNC). The initial value given to this counter is given via the signal lines 8A1 to 8A24 and is equal to the value given to the counters 6A1 to 6A24.

As described above, according to the present embodiment, the common unit 3 outputs only two frame signals and two channel clocks, respectively, through the four signal lines for generating the channel pulse. Compared with a book, the number of signal lines is greatly reduced, and the number of connector pins is also greatly reduced. Therefore, the connector of the common unit 3 is downsized, and the common unit 3 itself can be downsized. Further, the channel portions 2A1 to 2A24 are respectively connected to the above four signal lines and five (5 bit) signal lines 8A1 to 8A24 for setting an initial value, but the conventional number is four. Compared with, the number of connector pins need not be increased that much. In other words, the common part 3 from 48 pins to 4 pins can be downsized, and the channel parts 2A1 to 2A2 from 4 pins to 9 pins
Since 4 does not increase in size, the PCM terminal equipment can be downsized as a whole.

FIG. 2 shows a block diagram of essential parts of another embodiment of the present invention. In this embodiment, the channel sections 21 to 23 respectively output channel pulses for eight channels, which is different from the case where the embodiment of FIG. 1 outputs the channel pulse for each channel. Counter 41 of channel section 21-23
.About.43 have the same functions as the counters 6A1 to 6A24 in FIG.
The initial values given to the counters 41 to 43 are 24 (11000) for the counter 41, 16 (10000) for the counter 42, and 8 (01000) for the counter 43, respectively. 8-bit shift registers 51 to 53 are connected to the counters 41 to 43, respectively. The shift registers 51 to 53 shift the input signals to the output terminals O0 to O7 and output them in synchronization with the pulse of the channel clock CHCLK.

In the channel clock generator having such a configuration, the counters 41 to 43 generate channel pulses by the 1st, 9th, and 17th pulses of the channel clock CHCLK, respectively, which are shifted and shifted. Output terminals O0 to O7 of registers 51 to 53 to PCM codec 1A1 to 1A24
Are sequentially output to. Also in this embodiment, since the number of signals output from the common unit 3 is four in consideration of transmission and reception, the connector can be downsized. Channel part 21
In the case of ~ 23, the output terminals are 8 × 2 = 16, but downsizing of the common part 3 (48 pins to 4 pins) leads to downsizing of the device.
The number of channel portions may be 4 or more.

In the above embodiment, the number of channels is set to 24 in Japan and the United States, but the present invention can be implemented if the number is 30 in Europe.
That is, by appropriately changing the number of counters and the initial value,
It can accommodate any number of channels.

[Effects of the Invention] As described above, according to the present invention, it is possible to reduce the size of the connector of the common part, and thus it is possible to reduce the size of the entire device.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of a PCM terminal device adopting an embodiment of the present invention, FIG. 2 is a block diagram of a main part of another embodiment of the present invention, and FIG. 3 is a multiplexed data and frame signal. And the channel clock, and FIG. 4 is a diagram for explaining the operation of the PCM codec. 1,1A1 to 1A24 …… PCM codec 2A1 to 2A24,21 to 23 …… Channel section 3 …… Common section 4,5,7A1 to 7A24,8A1 to 8A24 …… Signal line 6A1 to 6A24,41,43 …… Counter 31 …… Frame signal generating means 32 …… Channel clock generating means 51 to 53 …… Shift register

Claims (1)

(57) [Claims] 1. A frame signal generating means for generating a frame signal for instructing the start of one frame including a predetermined number N of channels, and a channel clock generating for generating a channel clock for instructing the start of each channel of the one frame. And a common part connected to the common part, initialized by the frame signal generated by the frame signal generating means, counted up by the channel clock generated by the channel clock generating means, and set respectively. A counter that outputs a pulse at the counted count of the initial value,
A shift register which shifts the pulse output from the counter by the channel clock generated by the channel clock generating means and sequentially outputs from the M output terminals, and is output from each output terminal of the shift register. A channel pulse generator characterized in that each pulse is applied to a corresponding one-channel PCM codec.