JPH05292052A - Bit multiplexing/byte multiplexing conversion circuit - Google Patents

Abstract

PURPOSE:To obtain the bit multiplexing/byte multiplexing conversion circuit which can perform bit multiplexing/byte multiplexing conversion irrelevantly to are increase or decrease in signal multiplicity. CONSTITUTION:This circuit consists of a 1/n frequency division part which outputs a pulse LP having the number (n) of bits and a 1/n period, an (n)-bit shift register 1 which shifts the bit-multiplexed input data IN by (number (n) of channelsX1 byte), a setting/resetting control part 7 which receives the respective shifted data, and outputs an H-level S signal and an L-level R signal at the time of an H level or an L-level S signal and an H-level R signal at the time of an L level, a loading timing control part 8 which inputs the pulse LP and outputs an H pulse only by one bit of the S signal or R signal at the time of H or output L-level S signal and R signal at the time of L, and an output shift register 9 which inputs the S signal and R signal from the control part 8 to corresponding FFs and shifts them with a master clock to obtain byte- multiplexed data OUT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit multiplex / byte multiplex conversion circuit in a high-order group demultiplexer for handling high-order group signals. In recent years, there has been a remarkable increase in signal multiplicity in transmission equipment. Particularly, with the spread of optical synchronous transmission lines such as FLM and NNI, there is a tendency to increase more and more. The increase in signal multiplicity means an increase in transmission speed, and as a result, a multiplex transmission means capable of high-speed signal multiplexing is required.

According to the present invention, in a high-speed signal multiplexing circuit for constituting the above-mentioned multiplex transmission means, conventional bit multiplexing (BIT INTERLEAVE MUX) data to be multiplexed in bit units,
BYTE INTERLEAVE
The present invention relates to a bit multiplex / byte multiplex conversion (or inverse conversion) circuit for converting to MUX) data, and the present invention is a SON.
ET, CCITT compliant equipment FLM, NNI
Etc. can be used.

[0003]

2. Description of the Related Art FIG. 5 is a block diagram for explaining a conventional example, and FIG. 6 is a signal timing chart for the configuration of FIG.
In FIG. 5, 1 is a 24-bit shift register, 2 is a 24-bit latch circuit, and 3 is n: 1 (in this example, 24:
1) a selection circuit, 4 a 1/24 frequency divider circuit, 5 a selection pulse generation circuit, and 6 a flip-flop.

As shown in FIG. 6, the master clock MC
Is a clock output from a microprocessor (not shown) at a constant cycle, and all signal timings are performed with reference to this master clock MC. That is, the master clock MC is input to the 24-bit shift register 1, the 1/24 frequency dividing circuit 4, the selection pulse generating circuit 5, the flip-flop 6, and the like.

Input data IN is sequentially input to the 24-bit shift register 1, for example, in the order of channels as shown in the figure. From this shift register 1, D01, D
As indicated by 02, ---, D24, the input data shifted by the master clock MC is output. These data D01, D02, ---, D24 are input to the 24-bit latch circuit 3. On the other hand, the 1/24 frequency divider circuit 4 supplies the control pulse to the 24-bit latch circuit 5 at a period of 1/24 of the master clock MC.
The bit latch circuit 2 outputs the data D01, D02, ---, D24 latched based on this control pulse to the 24-to-1 selection circuit 3.

Further, as shown in the figure, the selection pulse generating circuit 5 supplies the selection pulses φ1 to φ24 sequentially shifted based on the master clock MC to the 24-to-1 selection circuit 3. Therefore, the 24-to-1 selection circuit 3 outputs the input data only when the selection pulses .phi.1 to .phi.24 are input at the high level, so that the output data OUT multiplexed for each channel is flip-flopped as shown in the figure. Output via 6. In this example, the case where the multiplicity n = 3 is described.

[0007]

In the above-mentioned conventional circuit, n is used.
Since the to-one selection circuit (24-to-1 selection circuit in this example) is used, the delay due to the circuit element increases, and it becomes difficult to secure a speed margin as the multiplicity n increases. .. This will be explained below. FIG. 7 is a signal timing chart for explaining the problems of the conventional circuit described above.
As shown in the figure, multiplex data MUX is obtained by multiplexing the data 1 to 4 with the selection pulses φ1 to φ4 at the timing of the master clock MC. In the figure, is the fluctuation range of data, sp is the setup time of the retiming FF, and hd is the hold time of the retiming FF. Then, sp + hd is a retiming FF prohibition region.

By the way, when the signal multiplicity increases (that is, the signal speed increases), not only the data cycle (1 bit width) becomes shorter, but also the number of gate stages of the circuit for data multiplexing increases. become. In the conventional circuit shown in the figure, the ratio of the range to the data width (1 bit) increases, so that the change point of the data enters the prohibited area (sp + hd) of the flip-flop FF for retiming the data. , Read the data twice,
Alternatively, there is a problem that skipping of data is likely to occur.

An object of the present invention is to provide a bit multiplex / byte multiplex conversion circuit (or its inverse conversion circuit) capable of bit multiplex / byte multiplex conversion regardless of increase / decrease in signal multiplicity.

[0010]

FIG. 1 is a block diagram showing the principle of the present invention. The present invention is a bit-multiplexing / byte-multiplexing converting circuit in a high-order group demultiplexing apparatus that handles a high-order group signal, and has a bit number n synchronized with a master clock MC.
The 1 / n frequency divider 4 which outputs a load pulse LP of 1 / n cycle and the bit multiplexed input data IN are received, and the input data is shifted by the number of channels n × 1 byte based on the master clock MC. The shift data is received from the bit shift register 1 and the n-bit shift register, and when the shift data is at the high level H, the set signal S at the high level and the reset signal R at the low level L are output, and the shift data is At the low level, the set / reset control unit 7 that outputs the low level set signal and the high level reset signal, and the load pulse are input,
Load timing that outputs a high level pulse for only one bit of the set signal and the reset signal when the load pulse is at a high level, and outputs a low level for both the set signal and the reset signal when the load pulse is at a low level It is composed of a control unit 8 and a plurality of flip-flops with set / reset. The set signal and the reset signal from the load timing control unit are input to the corresponding flip-flops, which are sequentially shifted by the master clock, and byte multiplexed data is obtained. And an output shift register 9 for obtaining OUT.

Then, the set / reset controller 7 is
It has a plurality of set / reset control circuits S / R-CNT corresponding to each output of the bit shift register, each set / reset control circuit is composed of one inverter INV, and the load timing control unit 8 Has a plurality of load timing control circuits LT-CNT corresponding to each set / reset control circuit, each load timing control circuit is composed of two AND gates, and one input of one AND gate is 24 Each output from the bit shift register is directly received, one input of the other AND gate receives the output of the inverter, and both AND gates receive the load pulse.

[0012]

FIG. 2 is a block diagram of an embodiment of the present invention. Figure 2
In the above, 1 is a 24-bit shift register, which shifts bit-multiplexed data by the number of channels × 1 byte. In this figure, the case where the number of channels = 3 is described as an example, so that the shift is 24 bits. Also, 4
Is a 1/24 frequency divider circuit, which is composed of a counter, for example, and generates the load pulse LP at a period of 1/24 of the master clock MC.

Reference numeral 7 denotes a set / reset control unit, which is 24
Bit shift register outputs Q01, Q02, ---
-Set / reset control circuit S / R corresponding to Q24
If the data Q01, Q02, ---, Q24 output from the 24-bit shift register 1 has a high level "H", the set signal S = H and the reset signal R = L are set, and a 24-bit If the data Q01, Q02, -----, Q24 output from the shift register 1 is low level "L", the set signal S = L, the reset signal R
= H is output.

Reference numeral 8 is a load timing control unit, which includes a load timing control circuit LT-CNT corresponding to each set / reset control circuit. This load timing control unit uses the load pulse L generated by the 1 / n frequency dividing circuit 4.
P / P from the set / reset control unit 7 according to P.
In order to add control to the reset signal, when the load pulse LP is "H", only one bit of the set / reset signal outputs an "H" pulse, and the load pulse from the 1 / n frequency dividing circuit 4 is outputted. When LP is "L", both set / reset signals output "L". That is, set /
The reset signals are both prevented from being "H".

Reference numeral 9 denotes an output shift register, which is set / set.
24 flip-flops FF with reset are provided. The set / reset signal from the load timing controller 8 is input to the set / reset terminal of each flip-flop. Also, the bit arrangement at this time is arranged so as to be the arrangement of byte multiplexed data. That is, here, the data is latched in each flip-flop by the load pulse LP from the 1/24 frequency dividing circuit 4, and the data is shifted and read by the master clock MC.

FIG. 3 shows a concrete circuit example of the set / reset control circuit and the load timing control circuit of the present invention.
As shown, each set / reset control circuit is composed of one inverter, and each load timing control circuit is AN.
It is composed of two D gates. Each output of the 24-bit shift register is directly input to one AND gate and is inverted and input to the other AND gate by the inverter INV. In this case, the direct input side becomes the set signal and the side via the inverter becomes the reset signal.

Since it is composed of an AND gate, for example, when the load pulse LP is "H", only one bit of the set / reset signal outputs a "H" pulse, and the 1 / n frequency dividing circuit. When the load pulse LP from 4 is "L", both set / reset signals are "L"
Is output. That is, both the set / reset signals are prevented from being "H".

FIG. 4 is a timing chart for explaining the operation of the present invention. The master clock MC is supplied from the microprocessor (not shown) as described above. Two
Outputs Q01 and Q0 from the 4-bit shift register 1
2, ---, Q24 are outputs D01, D02, ---, D in the conventional signal timing chart described in FIG.
Similar to 24. Then, serially multiplexed output data OUT is obtained from the output shift register 9 in accordance with "H" and "L" of the set / reset signal from the load timing control circuit.

[0019]

As described above, according to the present invention,
Since the data multiplexer is multiplexed by the shift register based on the master clock without configuring the data multiplexer with the n-to-1 selector circuit, a bit multiplex / byte multiplex conversion circuit which is advantageous in speed margin and capable of high speed operation, or An inverse conversion circuit can be provided.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a specific circuit example of a set / reset control circuit and a load timing control circuit of the present invention.

FIG. 4 is a timing chart explaining the operation of the present invention.

FIG. 5 is a block diagram illustrating a conventional example.

6 is a signal timing chart of the configuration of FIG.

FIG. 7 is a signal timing chart for explaining the problems of the conventional circuit.

[Explanation of symbols]

 1 ... 24-bit shift register 2 ... 24-bit latch circuit 3 ... 24-to-1 selection circuit 4 ... 1/24 frequency divider circuit 5 ... Selection pulse generation circuit 6 ... Flip flop 7 ... Set / reset control unit 8 ... Load Timing control unit 9 ... Output shift register

Claims (3)

[Claims] 1. A bit-multiplexing / byte-multiplexing converting circuit in a high-order group multiplexer / demultiplexer that handles a high-order group signal, wherein 1 / n of the number of bits n is synchronized with a master clock (MC).
The 1 / n frequency divider (4) that outputs a load pulse (LP) of n cycles and the bit-multiplexed input data (IN) are received, and the input data is transmitted based on the master clock (MC). An n-bit shift register (1) that shifts by × 1 byte, and each shift data from the n-bit shift register, and when the shift data is high level (H), a high level set signal (S) And a set / reset control section (7) which outputs a low level (L) reset signal (R) and outputs a low level set signal and a high level reset signal when the shift data is low level. When a load pulse is input and the load pulse is at a high level, one of the set signal and the reset signal
A load timing control unit (8) that outputs a high level pulse only for bits and outputs a low level for both the set signal and the reset signal when the load pulse is at a low level, and a plurality of flip-flops with set / reset An output shift register (9) configured to input the set signal and the reset signal from the load timing control unit to the corresponding flip-flops and sequentially shift by the master clock to obtain byte multiplexed data (OUT)
A bit multiplex / byte multiplex conversion circuit in a high-order group multiplex / separation device comprising: 2. The set / reset control section (7) has a plurality of set / reset control circuits (S / R-CNT) corresponding to each output of the n-bit shift register, and each set / reset control circuit (S / R-CNT). The reset control circuit is a single inverter (IN
The bit multiplex / byte multiplex conversion circuit according to claim 1, which is composed of V). 3. The load timing control section (8) has a plurality of load timing control circuits (LT-CNT) corresponding to the respective set / reset control circuits, and each load timing control circuit has two load timing control circuits. AND gates, one input of one AND gate directly receives each output from the 24-bit shift register, one input of the other AND gate receives the output of the inverter, and which AND gate 3. The bit-multiplexing / byte-multiplexing conversion circuit according to claim 1, which also receives the load pulse.