JP3310694B2 - M-sequence pseudo-random signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an M-sequence pseudo-random signal generator for generating an M-sequence (maximum long-period sequence) PN signal (pseudo-random signal), and more particularly to an M-sequence outputting a high-frequency PN signal. The present invention relates to a pseudo-random signal generator.

[0002]

2. Description of the Related Art When testing for the presence or absence of a code error occurring in various digital devices incorporated in a digital transmission system, an M sequence (maximum long period sequence) PN signal (Pseudo Random Noise Signal) is generally used as a test signal. : Fake
(Similar random signal). This test signal PN
The signal frequency must be higher than the frequency of various digital signals input / output to / from the device under test in a normal operating state.

[0003] A PN signal generating circuit for outputting an M-sequence PN signal having a bit period of (2 ⁿ -1) generally comprises n registers connected in series and a plurality of exclusive OR circuits. Have been. Therefore, it is necessary to use high-performance parts that operate accurately at high frequencies corresponding to the various digital signals described above for these constituent members.
Manufacturing costs rise significantly.

In order to eliminate such inconvenience, FIG.
An M-sequence pseudo- random signal generator having the configuration shown in FIG. The clock signal a input from the input terminal 1 and having at least the frequency f ₀ higher than the frequency of the digital signal input / output to / from the device under test is
/ M. The output signal b of the frequency divider 2 having the frequency (f ₀ / M) is input to the PN signal generation circuit 3.

As shown in FIG. 5, for example, this PN signal generation circuit 3 is a single circuit that performs an exclusive OR operation of serial n-stage shift registers 4 and respective outputs of a plurality of registers 4 a constituting the shift registers 4. Alternatively, it is composed of a plurality of EXOR gates (exclusive OR circuits) 4b. Then, by applying the clock signal (output signal b), a PN signal c having a bit cycle of (2 ⁿ -1) is output from the output terminal 4e.

Each output signal of each of the n registers 4a of the PN signal generation circuit 3 is input to the next out-of-phase PN signal generation circuit 5. As shown in FIG. 6, for example, the out-of-phase PN signal generating circuit 5 includes a plurality of EXOR gates 5a which take the exclusive OR of each output signal from the PN signal generating circuit 3.
It is composed of

Here, the operation principle of the out-of-phase PN signal generation circuit 5 will be described.

Generally, as shown in FIG. 6, in a PN signal generating circuit 3 comprising n registers 4a1, 4a2, 4a3,..., 4an-1, 4an, an output signal from an output terminal 4e is generated by the PN signal generating circuit. The reference PN signal PN0 of the circuit 3 is used. However, each signal extracted from each register is also a PN signal. The PN signal PNi taken from an arbitrary register 4ai is delayed by one bit (delayed) compared to the PN signal PNi-1 taken from the immediately preceding register 4ai-1.
It was) a PN signal. That is, each register 4a1, 4a
Each of the PN signals PN1, PN2, PN3,..., PNn (= PN0) output from 2, 4a3,.
A PN signal having the same bit period and bit pattern as (2 ⁿ -1) but different bit phases is obtained.

Then, as shown in FIG. 6, each PN signal is synthesized by an EXOR gate 5a.
The signal PG is also a PN signal whose phase is shifted by a predetermined bit from the reference PN signal PN0. in this way,
Each of the PN signals PN1, PN2, PN3,..., PN output from each of the registers 4a1, 4a2, 4a3,.
By synthesizing the signal as it is or by using one EXOR gate 5a or a plurality of EXOR gates 5a, the PN whose bit phases are shifted by various numbers of bits is synthesized.
A signal can be created. That is, the bit phases are shifted from each other, and a PN signal having one cycle of (2 ⁿ -1) is obtained.

In other words, conversely, in order to obtain a PN signal having a bit phase different by an arbitrary number of bits, a number of E are determined by using the PN signal of which register and the PN signal of which register.
Whether to use the XOR gate 5e is uniquely determined.
For example, M PN signals PG1 whose bit phases are shifted by (2 ⁿ -1) / M from the reference PN signal PN0.
, PG2,..., PGM-1 and PGM can be created. FIG. 7 shows each PN signal PG1, PG2,.
The phase relationship of M is shown.

M output from the out-of-phase PN signal generation circuit 5 and having bit phases shifted by (2 ⁿ -1) / M from each other.
The PN signals PG1, PG2,..., PGM are input to the next multiplexer 6. The multiplexer 6 synchronizes with the frequency f ₀ / M of the output signal b of the frequency divider 2 from the out-of-phase PN signal generation circuit 5 to output the PN signals PG 1, PG 2,.
PGM is input and a clock signal a having a frequency f ₀ is applied. Then, the multiplexer 6 is parallel the M PN signal PG1, PG2, ..., converts PGM into one serial signal d of the frequency f _0.

[0012] As shown in FIG. 7, M at the frequency f ₀ of the M times
Since the values of the PN signals PG1, PG2,..., PGM are sequentially sampled, the serial signal d is also (2 ⁿ −
The final PN signal d having the bit period of 1) is output from the output terminal 7 to the outside (Japanese Patent Publication No. 49-1278).
No. 6). That is, the code speed of the PN signal d becomes equal to the frequency f ₀ of the clock signal a.

In the M-sequence pseudo- random signal generator constructed as described above, the PN signal generator 3 and the out-of-phase PN signal generator 5 are divided by the frequency divider 2 into 1 / M. Since the driving is performed at the frequency f ₀ / M, there is no need to use expensive components having a high frequency response, so that the manufacturing cost can be reduced.

[0014]

However, the M-sequence pseudo- random signal generator constructed as shown in FIG. 4 still has the following problems to be solved.

In recent years, in digital communication systems,
Signals transmitted through a communication line are multiplexed, and the frequency of each data signal is dramatically increased. And, for example,
In a standard called SDH (Synchronous Digital Hierarchy) for a synchronous interface of data communication, there is a data transmission speed reaching 10 Gbps. Therefore, the code rate (frequency) f _{0 of the} PN signal d output from the output terminal 7 must also exceed 10 Gbps.

The code rate (frequency) f _{0 of the} PN signal d
In order to further increase the PN signal generation circuit 3
In addition, it is necessary to increase the operation speed of the out-of-phase PN signal generation circuit 5 or increase the division ratio M of the frequency divider 2 and the multiplexing ratio M of the multiplexer 6.

As a specific example, the above-mentioned SDH STM-
Consider 64 transmission frequencies of 9953.28 Mbps.

In order to realize the PN signal d by the clock signal of this frequency f ₀ = 9953.28 MHz, when the frequency division ratio M of the frequency divider 2 is set to 8, the PN signal generation circuit 3 and the out-of-phase PN signal generation The frequency f ₀ / M of the output signal b input to the circuit 5 has a very high value of 1244.16 MHz. In order to operate normally at this frequency, it is necessary to use an ultra-high-speed logic circuit such as an ECL (emitter coupled logic) circuit for all circuit elements constituting the PN signal generation circuit 3. Since the ECL circuit consumes a large amount of power, it generates a large amount of heat, increases the circuit scale, and increases the manufacturing cost.

When the frequency division ratio M of the frequency divider 2 is set to 512, the frequency f ₀ / M of the output signal b input to the PN signal generation circuit 3 has a relatively low value of 19.44 MHz. At this frequency, PN signal generation circuit 3 and out-of-phase P
The N signal generation circuit 5 can be constituted by a low-speed logic circuit such as a CMOS. Further, power consumption and heat generation can be significantly reduced as compared with the case where the above-described ECL circuit is used.

However, the out-of-phase PN signal generating circuit 5 has M = 512 PN signals PG1 having different bit phases.
, PG2, .... Since we need to create PG512,
The circuit configuration becomes complicated and large-scale. The multiplexer 6 needs to multiplex M = 512 times from a code rate of 19.44 MHz to a code rate of 9953.28 MHz. Therefore, it is not possible to use a gate array or the like for the multiplexer 6, and it is necessary to configure all of the components with individual components. Therefore, the number of components increases, power consumption increases, and the circuit configuration becomes complicated. That is, if the frequency division ratio M of the frequency divider 2 is set to be larger than a certain limit, a problem such as a manufacturing cost also arises.

In the above-mentioned SDH, the STM
In addition to the -64 transmission rate of 9953.28 Mbps, the STM-16,1 having a transmission rate of 2488.32 Mbps, which is 1/4 of this transmission rate,
STM-4, 1/64 with a transmission rate of 622.08 Mbps of / 16
There is a standard such as STM-1 having a transmission speed of 155.52 Mbps.
Therefore, in order to obtain a PN signal d having frequencies corresponding to four types of transmission speeds conforming to all these standards, the frequency division ratio M is 8, 32, 128, and 512. Since the different-phase PN signal generation circuit 5 has a different circuit configuration for each frequency division ratio M, the circuit configuration of the entire M-sequence pseudo- random signal generator becomes complicated and large, and the manufacturing cost increases significantly.

The present invention has been made in view of such circumstances. By using two frequency dividers and two multiplexers, the operating frequency of the PN signal generation circuit can be reduced, and one multiplexer can be used. The multiplexing ratio can be reduced, and each circuit component can be composed of general low-speed circuit components.
Also, it can consist of highly integrated components such as gate arrays, power consumption can be reduced, and the manufacturing cost can be largely reduced M-sequence pseudo
It is an object to provide a similar random signal generator.

Further, by providing a PN signal selection circuit for selecting a plurality of PN signals output from the out-of-phase PN signal generation circuit in accordance with the input clock frequency, a simple configuration can be applied to a plurality of types of clock frequencies. An object of the present invention is to provide a useful M-sequence pseudo- random signal generator capable of outputting a PN signal and greatly expanding an applicable range.

[0024]

In order to solve the above-mentioned problems, in an M-sequence pseudo-random signal generation circuit according to the present invention, a first frequency divider for dividing a clock signal input from the outside by a frequency division ratio A is provided. , A second frequency divider for further dividing the output signal of the first frequency divider by the frequency division ratio B, and a period T of the M sequence driven by the output signal of the second frequency divider. P with
A PN signal generation circuit for outputting an N signal, and a first out-of-phase PN signal generation for outputting B PN signals having phases shifted by T / B with respect to the PN signal output from the PN signal generation circuit Circuit and A PN signals whose phases are shifted by T / A with respect to B PN signals whose phases are shifted by T / B output from the first out-of-phase PN signal generating circuit. A plurality of second out-of-phase PN signal generating circuits to be output and A × B PN signals having different phases output from the second out-of-phase PN signal generating circuits are respectively subjected to a first frequency division. A first multiplexer for converting the output signals of the mixer into A PN signals, and a second multiplexer for converting the A PN signals output from the first multiplexer into one PN signal with the clock signal. And two multiplexers.

In another aspect of the present invention, the above-described first and second frequency dividers, first and second multiplexers, PN
In addition to the signal generating circuit, Bm Pm signals whose phases are shifted by T / Bm with respect to the PN signal output from the PN signal generating circuit.
A first out-of-phase PN signal generating circuit for outputting an N signal, and B PN signals of the Bm PN signals output from the first out-of-phase PN signal generating circuit are arranged at equal phase intervals. a PN signal selection circuit for extracting, this PN signal selection circuit has been only B-number T / a to each other for each PN signal phase shifted in B-number for outputting the a-number of the PN signal a second extraction with An out-of-phase PN signal generating circuit and a dividing ratio B set in a second frequency divider and a PN signal of a PN signal selecting circuit so that the frequency of an output signal does not change even when the frequency of an input clock signal changes. Switching control means for switching the selection number B.

[0026]

In the M-sequence pseudo- random signal generator constructed as described above, the input clock signal is frequency-divided by the first and second frequency dividers into 1 / (A × B) and the PN signal is generated. Input to the generation circuit. Then, the first out-of-phase PN signal generation circuit outputs B PN signals whose phases are shifted by T / B with respect to the PN signal. The output B PN signals are:
Each P-phase signal is generated by a second out-of-phase PN signal generation circuit.
The N signals are converted into A PN signals whose phases are shifted by T / A from the N signals. The first multiplexer outputs A PN signals output from the B second different-phase PN signal generation circuits, that is, a total of (A × B) PN signals having different bit phases. Are converted into A PN signals having different bit phases. And the second
Converts the A PN signals into one PN signal. That is, this one PN signal is an M-sequence PN signal having a bit period T corresponding to the input clock signal frequency.

Further, the M-sequence pseudo-random signal generator according to another invention can correspond to the frequencies of a plurality of types of input clock signals. The frequency division ratio B of the second frequency divider when the frequency of the input clock signal is the maximum is Bm.
Further, the frequency division ratio B of the second frequency divider changes according to the frequency of the clock signal so that the PN signal generation circuit is always driven at a constant frequency. The first out-of-phase PN signal generation circuit outputs Bm PN signals whose phases are shifted by T / Bm from the PN signal.

Then, the first signal is selected by the PN signal selection circuit.
Bm PNs output from the out-of-phase PN signal generation circuit of
Among the signals, B PN signals having the frequency division ratio currently set in the second frequency divider are extracted at equal phase intervals. Further, Bm second different-phase PN signal generation circuits corresponding to the maximum clock frequency are provided. B PN signals selected as B of the Bm are input.

Thereafter, the operation is the same as that of the above-described invention. That is, in the present invention, the frequency division ratios B and P of the second frequency divider are set according to the frequency of the input clock signal.
Only by changing the selection number B of the N signal selection circuit and the multiplexing ratio B of the first multiplexer, a PN signal corresponding to the same frequency as the frequency of the input clock signal can be obtained.

[0030]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a schematic configuration of an M-sequence pseudo- random signal generator according to an embodiment.

The clock signal e having the frequency f ₀ input from the input terminal 11 is divided by the first frequency divider 12 into 1 /
A is divided. The output signal g of the first frequency divider 12 having the frequency (f ₀ / A) is further divided by the second frequency divider 13 at the frequency division ratio B, and then input to the PN signal generation circuit 14. You. Therefore, the output signal h of the second frequency divider 13
Is f ₀ / (A × B). In this embodiment, the frequency division ratio A of the first frequency divider 12 is a fixed value of 8 (A = 8). The frequency division ratio B of the second frequency divider 13 is specified by the control unit 15 composed of, for example, a microcomputer.

In the control unit 15, a frequency division ratio memory 15a shown in FIG. 2 is formed. This division ratio memory 15
In a, there are four types of standard STM described in SDH.
-1, STM-4, STM- 16, STM-64 4 type corresponding to each frequency f ₀ of the frequency division ratio B = 1,4,16,
64 (= Bm) are stored. Then, the operator of the apparatus uses the operation panel 16 to enter the four standards STM-1.
ＳSTM-64, a frequency division ratio B corresponding to this standard is set in the second frequency divider 13 . Since the frequency dividing ratio B is set in inverse proportion to the input frequency f ₀ , as is apparent from the frequency dividing ratio memory 15 a in FIG. 2, even if the input frequency f ₀ changes, the second frequency dividing ratio B is calculated. The frequency of the output signal h of the frequency divider 13 (f _S = 19.44 M
Hz) is a constant value.

The PN signal generation circuit 14 uses the P signal shown in FIG.
Like the N signal generating circuit 3, the circuit includes n registers and one or a plurality of EXOR gates. Then, n PN signals PN having different bit phases and having a bit period T of (2 ⁿ -1) are output from the output terminal of each register.
1, ..., PNN are output. , PNN output from the PN signal generation circuit 14 are input to a first first out-of-phase PN signal generation circuit 17.

The first out-of-phase PN signal generating circuit 17 outputs the PN signals PN1,...,... Output from the PN signal generating circuit 14, similarly to the out-of-phase PN signal generating circuit 5 shown in FIG.
PNN is composed of a plurality of EXOR gates that take the exclusive OR of each other. Then, as shown in FIG. 3, Bm PN signals PG1, PG2,..., PGBm whose bit phases are shifted from each other by (2 ⁿ -1) / Bm are output.

Note that Bm (= 64) is the clock signal e.
Is the frequency division ratio set in the second frequency divider 13 when the frequency f ₀ is set to the maximum value 9953.28 MHz. That is, Bm is the frequency division ratio B set in the second frequency divider 13.
Is the maximum value of Therefore, the bit phases are [(2 ⁿ
-1) / 64], the 64 PN signals shifted by
The signal is input to the signal selection circuit 18.

The number B equal to the frequency division ratio of the second frequency divider 13 specified by the control unit 15 is applied to the PN signal selection circuit 18. Then, the PN signal selection circuit 18
Of the Bm PN signals PG1, PG2,..., PGBm inputted from the out-of-phase PN signal
The N signals PH1, PH2,..., PHB are selected at equal phase intervals. For example, when B = 1 (STM-1), Bm (= 6
4) Any one of the four, if B = 4 (STM-4), a total of four every 16 and B = 16 (STM-16)
, B = 64 (STM-6
In the case of 4), all 64 are selected.

Each of the 64 output terminals of the PN signal selection circuit 18 is connected to a second out-of-phase PN signal generation circuit 19. Each of the second out-of-phase PN signal generation circuits 19 has the same configuration. When the PN signal PH is input, the input PN signal is bit-phased with each other as shown in FIG. Is [(2 ⁿ -1) / A
(= 8)] A (= 8) PN signals PJ1,
PJ2, ... Outputs PJA.

Therefore, the Bm (= 64) second
Among the B second out-of-phase PN signal generation circuits 19 selected by the PN signal selection circuit 18, the bit phase of each of them is [(2 ⁿ
-1) / B] each shifted PN signal PH1. …, PHB
Is entered.

The A (= 8) PN signals PJ1, PJ2,..., Each having a different phase, output from the selected B second different-phase PN signal generation circuits 19, respectively. PJA
Are input to the first multiplexer 20 as shown in FIG. The first multiplexer 20 has a total of (A × B) P bits having different bit phases.
The N signal PJ is input. The first multiplexer 20 converts each of the A PN signals input at the frequency f _S (= f ₀ / (A × B) ) into the frequency (f ₀ / A) of the output signal g of the first frequency divider 12. Performs time division multiplexing to convert the speed into A signals. Accordingly, the multiplexing ratio is B, and the A signals have bit periods (2 ⁿ -1) and frequencies (f ₀ / A) having different bit phases from each other, as shown in FIG.
PN signals PK1, PK2,...

The A PN signals PK 1, PK 1, output from the first multiplexer 20, whose bit phases are shifted from each other,
, PKA are input to the next second multiplexer 21. The second multiplexer 21 has a frequency (f
₀ / A), each of the A PN signals PK1, PK2
,.., PKA are time-division multiplexed at the frequency f ₀ of the clock signal e and converted into one signal j. Therefore, the multiplexing ratio is A, and one signal j has a final P with period (2 ⁿ -1) and frequency f _0, as shown in FIG.
N signal. Then, the final PN signal j is output from the output terminal 22.

In the M-sequence pseudo- random signal generator configured as described above, the frequency f ₀ of the clock signal e input to the input terminal 11 is equal to the first and second frequency dividers 12.1.
After being divided into 1 / (A × B) by 3 and input to the PN signal generation circuit 14, the PN signal generation circuit 1
4, and a first out-of-phase PN signal generation circuit 1 following this
7, the PN signal selection circuit 18 and each second out-of-phase PN signal generation circuit 19 are driven at a low frequency.

Therefore, these circuits can be constituted by ordinary low-speed logic circuits. Further, the second frequency divider 13 and the first multiplexer 20 can be constituted by high-speed logic circuits. The only components that need to operate at the same frequency f ₀ as the input frequency are the first frequency divider 12 and the second multiplexer 21.

Therefore, as compared with the conventional device which requires the main components such as the PN signal generation circuit 3 and the out-of-phase PN signal generation circuit 5 to be constituted by high-speed logic circuits, the high-speed operation in the whole device is realized. Since the number of logic circuits used is greatly reduced, power consumption and heat generation are reduced. In terms of manufacturing cost, etc., it is extremely excellent.

As a result, one multiplexer 6 in FIG. 4 is realized by the first and second two multiplexers 20 and 21 in the present invention. Therefore,
Since the multiplexing ratios A and B can be set low per unit, the circuit configuration of the entire multiplexer can be greatly simplified.

The same can be said for the out-of-phase PN generation circuit. In the out-of-phase PN generation circuit 5 of FIG. 4, it was necessary to create 512 PN signals having different bit phases, but in the present invention, the first out-of-phase P
The N generation circuit 17 may generate 64 PN signals,
Each second out-of-phase PN generation circuit 19 may generate eight PN signals. That is, since the circuits of the first and second out-of-phase PN generation circuits 17 and 19 can be simplified and standardized, the manufacturing cost of the whole out-of-phase PN generation circuit is greatly reduced.

Also, the control unit 15 variably controls the frequency division ratio B of the second frequency divider 13 so that the PN signal generation circuit 14
Always controlled to a constant value a frequency f _S of the input signal h, further, the number corresponding to the number of PN signal output from the first of the different phase PN signal generator 17 to the maximum frequency of the clock signal e Bm ( = 64). The PN signal selection circuit 18 selects B PN signals corresponding to the frequency f ₀ .

That is, even if the frequency f ₀ of the input clock signal e changes according to the SDH standards STM-1 to STM-64, the PN signal generation circuit 14 generates the first and second out-of-phase PN signals. There is no need to change the circuit configuration of the devices 17 and 19 at all.

As described above, one M-sequence pseudo- random signal generator generates P-signals corresponding to a plurality of types of frequencies f _0.
An N signal j can be obtained, and a code error test apparatus for a device under test in which a digital signal having a transmission rate of each standard in SDH is signal-processed can be realized.

The present invention is not limited to the embodiment described above. For example, one kind of code rate (frequency) f
_When it is sufficient to realize only a PN signal of ₀ , the frequency division ratio B of the second frequency divider 13 is a fixed value. Therefore, the number B of PN signals output from the first out-of-phase PN signal generation circuit 17
Is also fixed. Therefore, in this case, the first different phase P
The B PN signals output from the N signal generation circuit 17 may be directly input to the B second out-of-phase PN signal generation circuits 19. Therefore, the PN signal selection circuit 18 is not required. Further, the number of the second out-of-phase PN signal generation circuits 19 is also fixed to B.

As described above, one kind of code rate (frequency)
When only the PN signal of f ₀ is obtained, the circuit configuration can be further simplified.

[0051]

As described above, the M-sequence simulation of the present invention
In a similar random signal generator, two frequency dividers and two
Multiplexers are used. Therefore, the operating frequency of the PN signal generation circuit can be reduced, and the multiplexing ratio can be reduced for each multiplexer, so that each circuit component can be composed of general low-speed circuit components. As a result, each constituent member can be composed of highly integrated components such as a gate array, so that power consumption can be reduced and manufacturing costs can be significantly reduced.

Further, there is provided a PN signal selection circuit for selecting a plurality of PN signals output from the different phase PN signal generation circuit according to the input clock frequency. Therefore, even if the input clock frequency changes, each out-of-phase P
There is no need to change the configuration of the N signal generation circuit. Therefore,
P with a simple configuration and multiple code rates (frequency)
N signals can be output, and the applicable range can be greatly expanded.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an M-sequence pseudo- random signal generator according to one embodiment of the present invention;

FIG. 2 is a view showing storage contents of a frequency division ratio memory formed in a control unit of the apparatus of the embodiment;

FIG. 3 is a time chart showing the operation of the apparatus of the embodiment;

FIG. 4 is a block diagram showing a schematic configuration of a conventional M-sequence pseudo- random signal generator.

FIG. 5 is a block diagram showing a schematic configuration of a PN signal generation circuit;

FIG. 6 is a block diagram showing a PN signal generation circuit and an out-of-phase PN signal generation circuit;

FIG. 7 is a time chart showing the operation of a conventional M-sequence pseudo- random signal generator.

[Explanation of symbols]

11: input terminal, 12: first frequency divider, 13: second frequency divider, 14: PN signal generation circuit, 15: control unit, 16 ...
Operation panel, 17: first out-of-phase PN signal generation circuit, 1
8. PN signal selection circuit, 19: second out-of-phase PN signal generation time, 20: first multiplexer, 21: second multiplexer, 22: output terminal.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 7/58 H03K 3/84

Claims (2)

(57) [Claims] A first frequency divider for dividing a clock signal inputted from the outside by a frequency division ratio, and an output signal of the first frequency divider being further divided by a frequency division ratio; The second divider (1
3) and a PN signal generating circuit driven by the output signal of the second frequency divider and outputting a PN signal having an M-sequence period T
(14) a first out-of-phase PN signal generation circuit (17) that outputs B PN signals whose phases are shifted by T / B with respect to the PN signal output from the PN signal generation circuit; For each of the B PN signals shifted in phase by T / B output from the first out-of-phase PN signal generating circuit, A PN signals shifted in phase by T / A are output. A plurality of second out-of-phase PN signal generating circuits (19);
A having different phases output from the N signal generation circuit.
XB PN signals are converted into A PN signals with the output signal of the first frequency divider by a first multiplexer (2
0) and a second multiplexer (21) for converting the A PN signals output from the first multiplexer into one PN signal using the clock signal. . 2. A first frequency divider (12) for dividing a clock signal input from the outside by a frequency division ratio A, and a variable frequency divider for further dividing an output signal of the first frequency divider up to a maximum Bm. A second frequency divider (13) for dividing the frequency by the frequency ratio B; and a PN signal generating circuit (14) driven by an output signal of the second frequency divider and outputting a PN signal having an M-sequence cycle T. ), A first out-of-phase PN signal generation circuit (17) for outputting Bm PN signals whose phases are shifted by T / Bm with respect to the PN signal output from the PN signal generation circuit, and A PN signal selection circuit (18) for extracting B PN signals of the Bm PN signals output from one out-of-phase PN signal generation circuit at equal phase intervals;
B second out-of-phase PN signal generation circuits (19) for outputting A PN signals having phases shifted by T / A from each other for the B PN signals extracted by the signal selection circuit (19) And the P
B to which the PN signal extracted by the N signal selection circuit is input
A × B PN signals having different phases output from the respective second different-phase PN signal generation circuits are converted into A PN signals by using the output signal of the first frequency divider. A first multiplexer (20), and a second multiplexer for converting the A PN signals output from the first multiplexer into one PN signal using the clock signal.
(21) and a dividing ratio B set in the second frequency divider and a PN signal selection number of the PN signal selecting circuit so that the frequency of the output signal does not change even when the frequency of the input clock signal changes. An M-sequence pseudo-random signal generator comprising a switching control means (15) for switching B.