JPH04250713A - M series generating circuit - Google Patents

Abstract

PURPOSE:To decrease the designing man-hour and to reduce the number of kinds of LSIs by selecting outputs of parallel M series generating circuit with a selector and scrambling different signals by the same circuit. CONSTITUTION:In the case of selecting an STM-16 signal in the M series generating circuit, a selector 33 is selected to apply all outputs S1-S8 as a parallel signal, and in the case of selecting an STM-4, the selector 33 selects only the signals S1, S5 as a parallel signal so as to use a scrambling circuit in common. Then the scrambling circuit for the STM-4 signal for 2-parallel configuration and the scrambling circuit for the STM-16 signal for 8-parallel configuration are shared. Then the selector 33 selects all the signals S1-S8 when the STM-16 signal is scrambled by using a selective signal and the selector 33 selects the signals S1, S5 when the STM-4 signal is scrambled. The clocking speed of the M series generating circuit is the same for both signals.

Description

[Detailed description of the invention]

0001

[Field of industrial application] The present invention relates to an M-sequence generation circuit,
It is particularly suitable for parallel scrambling circuits or parallel descrambling circuits.

0002

2. Description of the Related Art An M sequence (maximum long period sequence) is a code generated by an n-stage feedback shift register as shown in FIG. The M sequence has a period of 2^n-1, and one period contains 2^(n-1) ``0''s and 2^(n-1)-1 ``1''s. Therefore, when n is large, the probability of appearance of "1" or "0" is approximately 0.5. Therefore, the M sequence can be regarded as a pseudorandom code. In digital transmission, such a pseudorandom code can be used as a scrambler to suppress consecutive zeros or consecutive "1"s in a signal to be transmitted by performing an exclusive OR with an information signal string.

However, the M-sequence generation circuit shown in FIG. 2 requires a clock having the same speed as the transmission line speed. In other words, the higher the transmission speed, the more expensive high-speed elements were required. For this reason, the signals are parallelized to reduce their speed and
Parallel scramblers have been devised that operate at low speeds. For example, AT&T Technical Journal
al, 65 (1986) pp123-136
describes how to construct a parallel scrambling circuit.

This document describes two methods for configuring a parallel scrambler. That is, pp1
23-125, Method I describes a method of parallelization using a transformation matrix from state n to n+1 of a shift register. Assuming that the number of parallel states is m, this is a method of finding a transformation matrix from state n to n+m, and configuring a parallel scrambling circuit using the transformation matrix. Also, pp1
Method II of 25-129 also creates a sequence of numbers extracted every certain number from the original M sequence.
This is a parallelization method that takes advantage of the property of the M sequence that it becomes a sequence. Especially in the case of Method II, the sequence created by extracting every power of 2 is the same generator polynomial,
The result is an M sequence that is simply out of phase with the original M sequence.

[0005]

In the new synchronous digital hierarchy recommended by CCITT, signals are scrambled using M sequences generated from the same generator polynomial in each hierarchy. However, because the signals have different speeds, it has been difficult to use the same scrambling circuit for each hierarchy signal. For example, 622.08
A scrambling circuit for STM-4 with a speed of Mbit/s could not be used for STM-16 with a speed of 2488.32 Mbit/s. Conversely, the STM-16 scrambling circuit is
Although it can be used for many applications, it is a waste as components that operate at high speed are expensive. By using a parallel scrambling method like the conventional technology mentioned above, it is possible to parallelize the signals and make the signal speed the same (the speed of STM-16 is exactly four times that of STM-4, so STM-16 can be connected in four parallels). Then, the speed of each parallelized signal will be the same as the speed of STM-4). However, since each hierarchy has a different number of parallel circuits, the same scrambling circuit cannot be used after all. That is, even if four STM-4 scrambling circuits were arranged, an STM-16 scrambling circuit could not be constructed. Therefore, it was necessary to design a separate scrambling circuit for each hierarchy, and the circuits could not be shared.

An object of the present invention is to construct a scrambling circuit that operates at the same clock speed even when scrambling signals of different hierarchies.
An object of the present invention is to provide a sequence generation circuit.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a selector that can select codes necessary for scrambling signals in each hierarchy from code strings output from a parallel M-sequence generation circuit. has been established. The following describes how to select a code using the selector. below,
An example will be described in which a scrambling circuit is shared between 8 parallel STM-16 signals and 2 parallel STM-4 signals. If the number of parallels is chosen like this, the signal speed will be 311.04 Mb.
It/s is the same, and the clock speed of the M-sequence generation circuit can also be the same. The generating polynomial of M series is x^7 +
If x^6 + 1 is not used in parallel, a circuit can be constructed from the exclusive OR 11 and the shift register 22 as shown in FIG.

[0008] It is said that a code string created by selecting every power of 2 code string from a certain M-sequence code string is the same M-sequence, but is out of phase with the original M-sequence. It has a nature. A method of configuring a parallel scramble circuit that takes advantage of this property is shown in the paper cited in the prior art section above. In this configuration method, there is a relationship between the number of parallels m and the phase difference t of the M sequence applied to the parallelized signals, m・t (modulo p) = 1, where p is the period of the M sequence. To establish. 8 parallel for STM-16, STM-4
Now, if we use 2 parallels, the period of M series is p = 2^7
-1 = 127, so the phase difference is 1
6 and 64. Therefore, the M applied to adjacent parallelized signals is
If the phase difference of the sequence is set to 16, STM-16
If the scramble circuit of is set to 64, STM
-4 scramble circuit is created. The phase difference can be created using exclusive OR, and in the case of STM-16 it is as shown in Figure 3. In FIG. 3, the phase difference between S1 and S2 is 16, and the phase difference between S1 and S5 is 64. Therefore, if only S1 and S5 are selected by the selector 33 and applied to the signal, a two-parallel STM-4 scrambling circuit is obtained. That is, by selecting a code string with the selector 33, it becomes possible for STM-16 and STM-4 to share the same circuit and a scrambling circuit with the same clock speed. A shared scrambler configured in this manner is shown in FIG.

The principle of the present invention shown in FIG. 1 is a generalization of what has been described above. The present invention provides a basic M-sequence generation circuit 1
From the output, the phase difference generation circuit 2 creates M sequences with various phase differences, from which an appropriate code sequence is selected by the selector 3 and applied to the parallelized signal to perform scrambling and descrambling. It is something to do.

0010

[Operation] By allowing the output of the parallel M-sequence generation circuit to be selected by the selector as described above, it becomes possible to scramble different signals using the same circuit. In Figure 1, S
In the case of TM-16, select with the selector 33 so that all outputs from S1 to S8 are applied to parallel signals,
In addition, in the case of STM-4, by selecting only S1 and S5 (or another combination with a phase difference of 64 such as S2 and S6) with the selector 33 and applying them to the parallel signals, the scrambling circuit is activated. Can be shared. Although the case of 8 parallels and 2 parallels has been described here, other combinations, for example, 32 parallels and 4 parallels, can be constructed in the same way. Furthermore, the scrambling circuit can be shared not only between STM-16 and STM-4, but also between STM-1 and STM-4, or STM-1, STM-4, and STM-16.

Furthermore, since the descrambling circuit can have the same configuration as the scrambling circuit, the M-sequence generation circuit of the present invention is also effective in the descrambling circuit.

0012

[Examples] The present invention will be explained below with reference to Examples.

FIG. 4 is an explanatory diagram of Embodiment 1, in which two parallel STM-4 scramble circuits and eight parallel STM-4 scramble circuits are shown.
-16 scramble circuits are shared. A circuit was created using an ECL gate array with an operating speed of 400MHz. Here, the selector 33 is
Depending on the selection signal, when scrambling the STM-16 signal, all from S1 to S8 are passed through.
Also, when scrambling STM-4 signals, S
It operates to pass only 1 and S5. In both cases M
The clock speeds of the sequence generation circuits are the same. As a result, STM-4 and ST
It was possible to scramble two different M-16 signals.

FIGS. 4 to 6 show another embodiment 2 of the present invention. In this example, as in Example 1, two STs are parallelized.
M-4 scramble circuit and 8 parallel STM-1
Although the purpose is to share 6 scramble circuits, the output code can be selected using 5 types of selection signals from SS1 to SS5. Selection signal and selector SE
Table 1 shows the correspondence between the outputs from L1 and SEL2.

FIG. 5 shows an example in which this M-sequence generation circuit is used as an STM-4 scramble circuit, and FIG. 6 shows an example in which this M-sequence generation circuit is used as an STM-16 scramble circuit. All 400
It was made with an ECL gate array with an operating speed of MHz. Here, the shared scrambling circuit 44 is the same as in FIG. 4. In FIG. 5, SS1 is given as the selection signal and S1
and S5 to scramble the two parallel STM-4 signals. In FIG. 6, the 8 parallel STM-16 signals are divided into two, and the output from the shared scrambling circuit 44 is applied to each. The shared scrambling circuit 44 receives a selection signal SS2.
Then, SS5 divides S1 to S8 into two parts and outputs them according to the above table. The portion surrounded by dotted lines here is exactly the same as the circuit in FIG. 5. According to this embodiment, when 8 parallel STM-16 signals are processed by 4 LSIs, 2 parallel each, the same circuit can be used for the scrambling circuit in each LSI. When used, the operation of each scrambling circuit can be selected using a selection signal.

In the case of the second embodiment, an STM-16 scramble circuit can be constructed using four STM-4 scramble circuits. Therefore, another L
There is no need to design SI, reducing design man-hours and LS
A decrease in the number of I varieties was observed.

Although the embodiments have been described above regarding the scrambling circuit, since the descrambling circuit has the same circuit configuration as the scrambling circuit, the present invention can be similarly applied to the descrambling circuit. Further, even in the case of a parallel number other than the above, the present invention can be applied as long as the parallel number is a power of 2.

[0018]

According to the present invention, even when signals of different hierarchies are scrambled, a common circuit can be used, so that there are effects such as a reduction in design man-hours and a reduction in the number of LSI types.

[0019]

[Brief explanation of the drawing]

[Figure 1] Basic principle circuit of the present invention

[Figure 2] Scramble circuit when not parallelized

[Figure 3]
8 parallel scramble circuit

FIG. 4: Shared scrambling circuit of the first embodiment of the present invention

FIG. 5 A shared scrambling circuit according to a second embodiment of the present invention.

FIG. 6: When the second embodiment of the present invention is used as an STM-4 scrambling circuit

[Figure 7] When the second embodiment of the present invention is used as an STM-16 scrambling circuit

[Explanation of symbols]

1 Basic M-sequence generation circuit 2 Phase difference creation circuit 3 Selector 11 Exclusive OR 22 Shift register 33 Selector 44 Shared scramble circuit

Claims (2)

[Claims] 1. An M-sequence generation circuit, characterized in that the M-sequence generation circuit is provided with a selector that can select an appropriate code string from among the generated code strings. 2. A basic M-sequence generating circuit, a circuit for creating an M-sequence having a first to Nth phase difference from the output of the basic M-sequence generating circuit, and a circuit having a first to Nth phase difference. The M-sequence generating circuit according to claim 1, further comprising a circuit for selecting one or more M-sequences from the M-sequences.