JPH0619687A - M system pseudo random signal generator - Google Patents

Abstract

PURPOSE:To obtain a PN (pseudo random signal) signal of a high code signal (frequency) by using a low speed circuit part, in an M system pseudo random signal generator which generates the PN signal of an M system. CONSTITUTION:The frequency (f)0 of an inputted clock signal is frequency- divided by first and second frequency-dividers 12 and 13, and an PN signal generating circuit 14 is driven by the divided frequency. Next, B pieces of PN signals whose bit phases are shifted each other are prepared from the PN signals outputted from the PN signal generating circuit 14 by using a first different phase PN signal generating circuit 17, and A pieces of PN signals are prepared from the B pieces of PN signals by using plural second different phase PN signal generating circuits 19. Then, the AXB pieces of PN signals are converted into the A pieces of PN signals by a first multiplexer 20, and the A pieces of PN signals are converted into one final PN signal having the code speed (frequency) (f)0 by a second multiplexer 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an M-sequence pseudo-random signal generator for generating an M-sequence (maximum long-period sequence) PN signal (pseudo-random signal), and particularly to an M-sequence outputting a PN signal of high frequency. The present invention relates to a pseudo random signal generator.

[0002]

2. Description of the Related Art When testing the presence or absence of a code error occurring in various digital devices incorporated in a digital transmission system, a PN signal (Pseudo Random Noise signal) of M sequence (maximum long period sequence) is generally used as a test signal. : Pseudo random signal) is used. PN as this test signal
Naturally, the frequency of the signal needs to be higher than the frequencies of various digital signals input to and output from the device under test in the normal operating state.

A PN signal generating circuit for outputting an M series PN signal having a bit period of (2 ⁿ -1) is generally composed of n registers connected in series and a plurality of exclusive logic circuits. Has been done. Therefore, since it is necessary to use high-performance parts that accurately operate at high frequencies corresponding to the various digital signals described above for each of these constituent members,
Manufacturing costs rise significantly.

In order to eliminate such inconvenience, FIG.
An M-sequence pseudo-random signal generator having the configuration shown in is used. The clock signal a input from the input terminal 1 and having a frequency f ₀ higher than the frequency of at least the digital signal input to and output from the device under test is 1 by the frequency divider 2.
/ M is divided. The output signal b of the frequency divider 2 having the frequency (f ₀ / M) is input to the PN signal generation circuit 3.

As shown in FIG. 5, for example, the PN signal generating circuit 3 is a single n-stage shift register 4 and an exclusive OR of outputs of a plurality of registers 4a constituting the shift register 4. Alternatively, it is composed of a plurality of EXOR gates (exclusive OR circuits) 4b. Then, by applying the clock signal (output signal b), the PN signal c having a bit period of (2 ⁿ -1) is output from the output terminal 4e.

The output signals of the n registers 4a of the PN signal generation circuit 3 are input to the next out-of-phase PN signal generation circuit 5. The different-phase PN signal generating circuit 5 has a plurality of EXOR gates 5a for obtaining the exclusive OR of the output signals from the PN signal generating circuit 3, as shown in FIG.
It is composed of.

Here, the operation principle of the different phase PN signal generation circuit 5 will be described.

Generally, as shown in FIG. 6, in a PN signal generating circuit 3 consisting of n registers 4a1, 4a2, 4a3, ..., 4an-1, 4an, an output signal from an output terminal 4e is generated by this PN signal generating circuit. The reference PN signal PN0 of the circuit 3 is used. However, each signal taken out from each register is also a PN signal. The PN signal PNi taken out from the arbitrary register 4ai is a PN signal which is one bit ahead (advanced) in comparison with the PN signal PNi-1 taken out from the register 4ai-1 one before. That is, each register 4a1, 4a
The PN signals PN1, PN2, PN3, ..., PNn (= PN0) output from 2, 4a3 ,.
The PN signals have the same bit period and bit pattern of (2 ⁿ -1) but different bit phases.

Then, as shown in FIG. 6, each PN signal is synthesized by the EXOR gate 5a.
The signal PG is also a PN signal whose phase is shifted by a predetermined bit from the reference PN signal PN0. in this way,
PN signals PN1, PN2, PN3, ..., PN output from the registers 4a1, 4a2, 4a3, ..., 4an-1, 4an
By combining n as it is or by using one EXOR gate 5a or a plurality of EXOR gates 5a to synthesize signals, PNs shifted in bit phase by various numbers of bits
It is possible to create a signal. That is, (2 ⁿ -1) PN signals whose bit phases are shifted from each other are obtained.

On the contrary, in order to obtain a PN signal having a different bit phase by an arbitrary number of bits, the PN signal of which register and the PN signal of which register are used to determine the number of Es.
Whether to use the XOR gate 5e is uniquely determined.
For example, M PN signals PG1 whose bit phases deviate from each other by (2 ⁿ -1) / M with respect to the reference PN signal PN0.
, PG2, ..., PGM-1, PGM can be created. FIG. 7 shows the PN signals PG1, PG2, ..., PG
The phase relationship of M is shown.

M output from the out-of-phase PN signal generating circuit 5 having bit phases shifted by (2 ⁿ -1) / M from each other.
The PN signals PG1, PG2, ..., PGM are input to the next multiplexer 6. In the multiplexer 6, the PN signals PG1, PG2, ..., Synchronized with the frequency f ₀ / M of the output signal b of the frequency divider 2 from the different phase PN signal generating circuit 5.
PGM is input and the clock signal a having the frequency f ₀ is applied. The multiplexer 6 converts the M parallel PN signals PG1, PG2, ..., PGM into one serial signal d having a frequency f ₀ .

As shown in FIG. 7, M times the frequency f ₀
Since the values of the individual PN signals PG1, PG2, ..., PGM are sampled in order, the serial signal d is also (2 ⁿ −
The final PN signal d having the bit period 1) is output from the output terminal 7 to the outside (Japanese Patent Publication No. Sho 49-1278).
No. 6). That is, the code rate of the PN signal d becomes equal to the frequency f ₀ of the clock signal a.

In the M-sequence pseudo-random signal generator thus constructed, the PN signal generating circuit 3 and the out-of-phase PN signal generating circuit 5 are frequency-divided by the frequency divider 2 to 1 / M. Since it is driven at the frequency f ₀ / M, it is not necessary to use expensive components having a high frequency response, so that the manufacturing cost can be reduced.

[0014]

However, the M-sequence pseudo-random signal generator configured as shown in FIG. 4 still has the following problems to be solved.

In recent years, in digital communication systems,
The signals transmitted through the communication lines are multiplexed, and the frequency of each data signal has dramatically increased. And, for example,
In a standard called SDH (Synchronous Digital Hierarchy) in a synchronous interface for data communication, there is a standard in which the data transmission rate reaches 10 Gbps. Therefore, the code rate (frequency) f _{0 of the} PN signal d output from the output terminal 7 must also exceed 10 Gbps.

The code rate (frequency) f _{0 of} this PN signal d
In order to further raise the
It is necessary to increase the operating speed of the different phase PN signal generating circuit 5, or increase the frequency division ratio M of the frequency divider 2 and the multiplexing ratio M of the multiplexer 6.

As a concrete example, the above-mentioned SDH STM-
Consider 64 transmission frequencies of 9953.28 Mbps.

In order to realize the PN signal d by the clock signal of the frequency f ₀ = 9953.28 MHz, if the frequency division ratio M of the frequency divider 2 is set to 8, the PN signal generation circuit 3 and the different phase PN signal generation are generated. The frequency f ₀ / M of the output signal b input to the circuit 5 is 1244.16 MHz, which is a very high value. In order to operate normally at this frequency, it is necessary to use an ultra-high speed logic circuit such as an ECL (emitter coupled logic) circuit for all circuit elements constituting the PN signal generation circuit 3. Since this ECL circuit consumes a large amount of power, it generates a large amount of heat, the circuit scale also increases, and the manufacturing cost increases.

When the frequency division ratio M of the frequency divider 2 is set to 512, the frequency f ₀ / M of the output signal b input to the PN signal generation circuit 3 becomes a relatively low value of 19.44 MHz. At this frequency, the PN signal generating circuit 3 and the different phase P
The N signal generation circuit 5 can be composed of a low speed logic circuit such as CMOS. Further, the power consumption and the heat generation amount can be significantly reduced as compared with the case of using the above ECL circuit.

However, the out-of-phase PN signal generation circuit 5 has M = 512 PN signals PG1 having different bit phases.
, PG2, .... Since we need to create PG512,
The circuit configuration becomes complicated and large-scale. Also, the multiplexer 6 needs to multiplex M = 512 times from the code rate of 19.44 MHz to the code rate of 9953.28 MHz. Therefore, it is not possible to use a gate array or the like for the multiplexer 6, and it is necessary to configure all of them with individual parts. Therefore, the number of parts increases, power consumption increases, and the circuit configuration becomes complicated. That is, if the frequency division ratio M of the frequency divider 2 is set to be larger than a certain limit, problems such as manufacturing cost will occur.

In the SDH described above, the STM
-64 transmission rate of 9953.28 Mbps, 1/4 of this transmission rate of 248.832 Mbps STM-16,1
/ 16 transmission speed 622.08 Mbps STM-4, 1/64
There are standards such as STM-1 with a transmission speed of 155.52 Mbps.
Therefore, in order to obtain the PN signal d having the frequencies corresponding to the four types of transmission rates that conform to all of these standards, the frequency division ratio M becomes 8,32,128,512. Since the different-phase PN signal generation circuit 5 has a different circuit configuration for each frequency division ratio M, the circuit configuration of the entire M-sequence pseudo-random signal generation device becomes complicated and large, and the manufacturing cost increases significantly.

The present invention has been made in view of the above circumstances, and by using two frequency dividers and two multiplexers, the operating frequency of the PN signal generating circuit can be reduced and one multiplexer can be used. The per-multiplexing ratio can be reduced, and each circuit component can be composed of general low-speed circuit parts,
Another object of the present invention is to provide an M-sequence pseudo-random signal generator that can be configured with highly integrated components such as a gate array, can reduce power consumption, and can significantly reduce manufacturing costs.

Further, by providing a PN signal selection circuit for selecting a plurality of PN signals output from the different-phase PN signal generation circuit according to the input clock frequency, a simple configuration can be applied to a plurality of types of clock frequencies. It is an object of the present invention to provide a useful M-sequence pseudo-random signal generator capable of outputting a PN signal and greatly expanding the range of application.

[0024]

In order to solve the above problems, in the M-sequence pseudo-random signal generating circuit of the present invention, the first frequency division for dividing the clock signal inputted from the outside by the frequency division ratio A is performed. And a second frequency divider that further divides the output signal of the first frequency divider by a frequency division ratio B, and is driven by the output signal of the second frequency divider. With P
A PN signal generating circuit that outputs an N signal, and a first out-of-phase PN signal generating circuit that outputs B PN signals that are out of phase by T / B with respect to the PN signal output from this PN signal generating circuit Circuit and A PN signals that are out of phase with each other by A / B PN signals that are out of phase with each other by T / B output from the first out-of-phase PN signal generation circuit. A plurality of second different-phase PN signal generating circuits and A × B PN signals having different phases output from the second different-phase PN signal generating circuits, respectively. A first multiplexer for converting into A PN signals by an output signal of a frequency divider and A in PN signals outputted from the first multiplexer are converted into 1 PN signal by the clock signal. It is provided with a second multiplexer.

In another invention, the above-mentioned first and second frequency dividers, first and second multiplexers, and PN
In addition to the signal generation circuit, Bm Ps whose phase is shifted by T / Bm with respect to the PN signal output from the PN signal generation circuit.
A first different-phase PN signal generating circuit that outputs an N signal, and B PN signals of the Bm PN signals output from the first different-phase PN signal generating circuit at equal phase intervals. The PN signal selection circuit to be extracted and the Bm second PN signals that output A PN signals that are out of phase with each other by T / A with respect to each of the B PN signals extracted by the PN signal selection circuit. The different phase PN signal generation circuit and the frequency division ratio B set in the second frequency divider and the PN signal of the PN signal selection circuit so that the frequency of the output signal does not change even if the frequency of the input clock signal changes. And a switching control means for switching the selection number B.

[0026]

In the M-sequence pseudo-random signal generator thus constructed, the input clock signal is divided into 1 / (A × B) by the first and second frequency dividers and the PN signal is obtained. Input to the generation circuit. Then, the first out-of-phase PN signal generation circuit outputs B PN signals whose phases are shifted by T / B with respect to the PN signal. Each of the B output PN signals is
Each P has a second out-of-phase PN signal generating circuit.
It is converted into A PN signals whose phase is shifted by T / A with respect to the N signal. The first multiplexer outputs the A PN signals output from the B second different-phase PN signal generation circuits, that is, the total (A × B) PN signals having different bit phases. Are converted into A PN signals each having a different bit phase. And the second
This A-number of PN signals is converted into one PN signal by the multiplexer. That is, this one PN signal becomes an M series PN signal having a bit period T corresponding to the input clock signal frequency.

The M-sequence pseudo-random signal generator of another invention can handle a plurality of types of input clock signal frequencies. Then, the frequency division ratio B of the second frequency divider when the frequency of the input clock signal is maximum is Bm.
Further, the frequency division ratio B of the second frequency divider changes according to the frequency of the clock signal so that the PN signal generating circuit is always driven at a constant frequency. The first out-of-phase PN signal generation circuit outputs Bm PN signals whose phases are shifted by T / Bm with respect to the PN signal.

Then, by the PN signal selection circuit, the first
Bm PNs output from the different phase PN signal generation circuit
Of the signals, B PN signals, which are the frequency division ratios currently set in the second frequency divider, are extracted at equal phase intervals. Further, the second different phase PN signal generating circuits are provided in Bm number corresponding to the maximum clock frequency. B selected PN signals are input to B of the Bm.

From this point onward, the operation is the same as that of the invention described above. That is, according to the present invention, the frequency division ratios B and P of the second frequency divider are set according to the frequency of the input clock signal.
A PN signal corresponding to the same frequency as the frequency of the input clock signal can be obtained only by changing the selection number B of the N signal selection circuit and the multiplexing ratio B of the first multiplexer.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of an M-sequence pseudo random signal generator of the embodiment.

The clock signal e having the frequency f ₀ input from the input terminal 11 is 1 /
Divided into A. The output signal g of the first frequency divider 12 having the frequency (f ₀ / A) is further divided by the second frequency divider 13 by the frequency division ratio B, and then input to the PN signal generation circuit 14. It Therefore, the output signal h of the second frequency divider 13
The frequency is f ₀ / (A × B). In this embodiment, the frequency division ratio A of the first frequency divider 12 is a fixed value of 8 (A = 8). Then, the frequency division ratio B of the second frequency divider 13 is designated by the control unit 15 including, for example, a microcomputer.

A frequency division ratio memory 15a shown in FIG. 2 is formed in the control unit 15. This division ratio memory 15
In a, the above-mentioned four types of standard STM in SDH
-1, STM-4, STM-16, STM-64 corresponding to each frequency f ₀ of four types of frequency division ratio B = 1, 4, 16,
64 (= Bm) is stored. Then, the operator of this apparatus uses the operation panel 16 to select the four standards STM-1.
When one of the standards STM-64 is input, the frequency division ratio B corresponding to this standard is set in the second frequency divider 13. This frequency division ratio B is set in inverse proportion to the input frequency f ₀ , as is apparent from the frequency division ratio memory 15a in FIG. 2, so that even if the input frequency f ₀ changes, the second frequency division ratio B is set. The frequency of the output signal h of the frequency divider 13 (f _S = 19.44 M
Hz) is a constant value.

The PN signal generating circuit 14 has the P shown in FIG.
Similar to the N signal generation circuit 3, it is composed of n registers and one or more EXOR gates. Then, from the output terminal of each register, n PN signals PN having a bit period T of (2 ⁿ −1) and different bit phases are provided.
1,…, PNN are output. The n PN signals PN1, ..., PNN output from the PN signal generating circuit 14 are input to the next first different phase PN signal generating circuit 17.

The first out-of-phase PN signal generating circuit 17 is similar to the out-of-phase PN signal generating circuit 5 shown in FIG. 4 in that each PN signal PN1, ...
It is composed of a plurality of EXOR gates that take the exclusive OR of PNNs. Then, as shown in FIG. 3, Bm PN signals PG1, PG2, ..., PGBm whose bit phases are shifted from each other by (2 ⁿ −1) / Bm are output.

Bm (= 64) is the clock signal e
Is a frequency division ratio set in the second frequency divider 13 when the frequency f ₀ is set to the maximum value of 9953.28 MHz. That is, Bm is the frequency division ratio B set in the second frequency divider 13.
Is the maximum value of. Therefore, the bit phases are [(2 ⁿ
-1) / 64] 64 PN signals shifted by the next PN signal
The signal is input to the signal selection circuit 18.

The PN signal selection circuit 18 is applied with a number B equal to the frequency division ratio of the second frequency divider 13 designated by the controller 15. Then, the PN signal selection circuit 18 has the first
, PGBm of Bm PN signals PG1, PG2, ..., PGBm input from the different phase PN signal generating circuit 17 of P
The N signals PH1, PH2, ..., PHB are selected at equal phase intervals. For example, when B = 1 (STM-1), Bm (= 6
4) Any one of the four, in the case of B = 4 (STM-4), a total of four every 16 pieces, B = 16 (STM-16)
In the case of, a total of 16 every four, B = 64 (STM-6
In the case of 4), all 64 are selected.

A second out-of-phase PN signal generating circuit 19 is connected to each of the 64 output terminals of the PN signal selecting circuit 18. All the second different-phase PN signal generation circuits 19 have the same configuration, and when the PN signal PH is input to each of the second PN signal generation circuits 19, as shown in FIG. Is [(2 ⁿ -1) / A
(= 8)] A (= 8) PN signals PJ1,
PJ2, ... Output PJA.

Therefore, this Bm (= 64) second
Among the different phase PN signal generation circuits 19 of B, only the second phase difference PN signal generation circuits 19 of B selected by the PN signal selection circuit 18 have bit phases [(2 ⁿ
-1) / B] each PN signal PH1. …, PHB
Is entered.

A (= 8) PN signals PJ1, PJ2, ..., Which are output from the selected B second different-phase PN signal generating circuits 19 and have different phases, respectively. PJA
Are respectively input to the first multiplexer 20 as shown in FIG. The first multiplexer 20 includes a total of (A × B) P Ps each having a different bit phase.
The N signal PJ is input. The first multiplexer 20 receives each of the A P Ps input at the frequency f _S (= f ₀ / A × B).
The frequency of the output signal g of the first frequency divider 12 (f ₀
/ A) performs time division multiplexing and performs speed conversion into A signals.
Therefore, the multiplexing ratio becomes B, and each of the A signals has a PN signal PK1 having a bit period (2 ⁿ -1) and a frequency (f ₀ / A) whose bit phases are different from each other, as shown in FIG. , PK2, ..., PKA.

A number of PN signals PK1 output from the first multiplexer 20 whose bit phases are shifted from each other,
PK2, ..., PKA are input to the next second multiplexer 21. The second multiplexer 21 has a frequency (f
₀ / A) each of A number of PN signals PK1 and PK2 input
, ..., PKA are time-division multiplexed at the frequency f ₀ of the clock signal e to be converted into one signal j. Therefore, the multiplexing ratio becomes A, and one signal j has a final P having a period (2 ⁿ −1) and a frequency f ₀ as shown in FIG.
It becomes the N signal. Then, the final PN signal j is output from the output terminal 22.

In the case of the M-sequence pseudo-random signal generator configured as described above, the frequency f ₀ of the clock signal e input to the input terminal 11 has the first and second frequency dividers 12.1.
After being divided into 1 / AB by 3 and inputted to the PN signal generating circuit 14, this PN signal generating circuit 14 and the following first different phase PN signal generating circuits 17 and P are provided.
The N signal selection circuit 18 and each second different phase PN signal generation circuit 19 are driven at a low frequency.

Therefore, these circuits can be constituted by a normal low speed logic circuit. Further, the second frequency divider 13 and the first multiplexer 20 can be configured by a high speed logic circuit. The first frequency divider 12 and the second multiplexer 21 are the only components that need to operate at the same frequency f ₀ as the input frequency.

Therefore, as compared with the conventional device in which the main constituent members such as the PN signal generating circuit 3 and the different phase PN signal generating circuit 5 need to be composed of the high speed logic circuit, the high speed in the whole device is seen. Since the number of points used in the logic circuit is greatly reduced, the power consumption and heat generation amount are reduced. Remarkably excellent in manufacturing costs.

Further, as a result, the single multiplexer 6 in FIG. 4 is realized by the first and second two multiplexers 20 and 21 in the present invention. Therefore,
Since the multiplexing ratios A and B per unit can be set low, the circuit configuration of the entire multiplexer can be greatly simplified.

The same applies to the out-of-phase PN generating circuit. In the out-of-phase PN generation circuit 5 of FIG. 4, it was necessary to create 512 PN signals each having a different bit phase, but in the present invention, the first out-of-phase P
The N generation circuit 17 may generate 64 PN signals,
Each second out-of-phase PN generation circuit 19 may create eight PN signals. That is, the circuits of the first and second different-phase PN generating circuits 17 and 19 can be simplified and standardized, so that the manufacturing cost of the entire different-phase PN generating circuit is significantly reduced.

Further, the control unit 15 variably controls the frequency division ratio B of the second frequency divider 13, and the PN signal generation circuit 14 is controlled.
Always controlled to a constant value a frequency f _S of the input signal h, further, the number corresponding to the number of PN signal output from the first of the different phase PN signal generator 17 to the maximum frequency of the clock signal e Bm ( = 64). Then, the PN signal selection circuit 18 selects B PN signals corresponding to the frequency f ₀ .

That is, even if the frequency f ₀ of the input clock signal e changes according to the SDH standards STM-1 to STM-64, the PN signal generation circuit 14 and the first and second different phase PN signal generations are generated. It is not necessary to change the circuit configuration of the devices 17 and 19 at all.

As described above, P corresponding to a plurality of types of frequencies f ₀ can be obtained by one M-sequence pseudo random signal generator.
The N signal j can be obtained, and the code error test apparatus for the device under test in which the digital signal having the transmission speed of each standard in SDH is processed is realized.

The present invention is not limited to the above embodiment. For example, one type of code rate (frequency) f
_When it is necessary to realize the PN signal of only ₀ , the frequency division ratio B of the second frequency divider 13 is a fixed value. Therefore, the number B of PN signals output from the first out-of-phase PN signal generation circuit 17
Is also fixed. Therefore, in this case, the first different phase P
The B PN signals output from the N signal generation circuit 17 may be directly input to the B second out-of-phase PN signal generation circuits 19. Therefore, the PN signal selection circuit 18 is not necessary. Also, the number of second different-phase PN signal generation circuits 19 installed is fixed to B.

Thus, one type of code rate (frequency)
When only the PN signal of f ₀ is obtained, the circuit configuration can be further simplified.

[0051]

As described above, in the M-sequence pseudo random signal generator of the present invention, two frequency dividers and two frequency dividers are used.
It uses a multiplexor. Therefore, the operating frequency of the PN signal generating circuit can be reduced, and the multiplexing ratio per multiplexer can be reduced, so that each circuit component can be configured by a general low-speed circuit component. As a result, each constituent member can be configured by a highly integrated component such as a gate array, power consumption can be reduced, and manufacturing cost can be significantly reduced.

Further, there is provided a PN signal selection circuit for selecting a plurality of PN signals output from the different phase PN signal generation circuit according to the input clock frequency. Therefore, even if the input clock frequency changes, each phase difference P
There is no need to change the configuration of the N signal generation circuit. Therefore,
P having a plurality of types of code rates (frequency) with a simple configuration
N signals can be output, and the applicable range can be greatly expanded.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an M-sequence pseudorandom signal generator according to an embodiment of the present invention,

FIG. 2 is a diagram showing stored contents of a frequency division ratio memory formed in a control unit of the apparatus of the embodiment.

FIG. 3 is a time chart showing the operation of the apparatus of the embodiment,

FIG. 4 is a block diagram showing a schematic configuration of a conventional M-sequence pseudo-random signal generator,

FIG. 5 is a block diagram showing a schematic configuration of a PN signal generation circuit,

FIG. 6 is a block diagram showing a PN signal generation circuit and a different phase PN signal generation circuit,

FIG. 7 is a time chart showing the operation of a conventional M-sequence pseudo-random signal generator.

[Explanation of Codes] 11 ... Input Terminal, 12 ... First Frequency Divider, 13 ... Second Frequency Divider, 14 ... PN Signal Generation Circuit, 15 ... Control Unit, 16 ...
Operation panel, 17 ... First out-of-phase PN signal generation circuit, 1
8 ... PN signal selection circuit, 19 ... Second different phase PN signal generation time, 20 ... First multiplexer, 21 ... Second multiplexer, 22 ... Output terminal.

Claims (2)

[Claims] 1. A first frequency divider (12) for dividing a clock signal input from the outside by a frequency division ratio A, and an output signal of the first frequency divider by a frequency division ratio B. The second frequency divider (1
3) and a PN signal generation circuit which is driven by the output signal of the second frequency divider and outputs a PN signal having a period T of M series
(14), a first out-of-phase PN signal generation circuit (17) for outputting B PN signals whose phase is shifted by T / B with respect to the PN signal output from this PN signal generation circuit, For each of the B PN signals output from the first out-of-phase PN signal generation circuit and out of phase with each other by T / B, output A PN signals that are out of phase with each other by T / A. A plurality of second different phase PN signal generation circuits (19) and each of the second different phase P
A output from the N signal generating circuit has different phases.
A first multiplexer (2) for converting × B PN signals into A PN signals by the output signal of the first frequency divider.
0) and a second multiplexer (21) for converting A PN signals output from the first multiplexer into one PN signal with the clock signal, and an M-sequence pseudo-random signal generator. . 2. A first frequency divider (12) for frequency-dividing an externally input clock signal with a frequency division ratio A, and an output signal of the first frequency divider which is further variable up to a maximum Bm. A second frequency divider (13) that divides at a frequency ratio B, and a PN signal generation circuit (14) that is driven by an output signal of the second frequency divider and outputs a PN signal having a cycle T of M series ), A first out-of-phase PN signal generation circuit (17) for outputting Bm PN signals whose phase is shifted by T / Bm with respect to the PN signal output from this PN signal generation circuit, and A PN signal selection circuit (18) for extracting B PN signals out of the Bm PN signals output from the different phase PN signal generation circuit 1 at equal phase intervals, and the PN signal selection circuit (18).
Bm second out-of-phase PN signal generation circuits (19) for outputting A PN signals whose phases are shifted from each other by T / A with respect to each of the B PN signals extracted by the signal selection circuit And the A × B PN signals having different phases output from each of the B second different-phase PN signal generation circuits to which the PN signal extracted by the PN signal selection circuit is input, First
The first multiplexer (20) for converting into A PN signals by the output signal of the frequency divider of A, and the A PN signals output from the first multiplexer are converted into one with the clock signal. A second multiplexer (21) for converting into a PN signal, and a frequency division ratio B set in the second frequency divider so that the frequency of the output signal does not change even if the frequency of the input clock signal changes. An M-sequence pseudo-random signal generator provided with a switching control means (15) for switching the PN signal selection number B of the PN signal selection circuit.