JPS5849058B2 - Inter-device data transmission synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inter-device data transmission synchronization method when data is transmitted between devices located at a relatively short distance.

When transmitting time-divided data from one device to another device through a cable that is, for example, several tens of meters long, there may be a clock phase shift between the devices or cable interference. It is necessary to synchronize the received data in consideration of transmission delay.

In contrast, conventionally, the transmitting side sends out data at appropriate timing taking into account cable delays, and the receiving side performs retiming to receive the data.

FIG. 1 is a block diagram showing the configuration of a conventional inter-device data transmission synchronization system.

In the figure, 1, 2, 3.4 are D type flip-flops (DF), 5 is a strap, 6 is a cable driver (DV), 7 is a multiplexed data line, 8 is a cable receiver (REC), 9 is a D type flip-flop (DF)
It is.

In addition, in the same figure, with the multiplexed data line 7 as an intermediate, the line within the dashed line on the left is the first device, and the line within the chain line on the right is the second device.
FIG. 2 shows a device in which data is transmitted from a first device to a second device in the conventional inter-device data transmission synchronization method shown in FIG. It is a time chart showing each part signal.

In the same figure, a indicates the case where the cable delay is small,
b shows the case where the cable delay is large.

Also, in Figures 1 and 2, 1, 2, 3.4 are the output data of DF1, 2, 3, 4, respectively, and 5 is the DV output data.
6 is the output data of REC8, 7 is the clock CLK2 of the second device, 8 is the output data of DF9.
Each of the

In the first device, data DPI, 2, 3.4 are sequentially passed through, and four types of outputs are obtained sequentially delayed by 1/2 of each period (Fig. 1, 1.2, 3.4).

In FIG. 1, CLK1 is the clock of the first device, and DF1, 2, 3.4 are operated by the clock CLK.

When the cable delay in the multiplexed data line 7 is small, as shown in FIG.
Output 4 is selected by strap 5 and input to DV6.

DV6 thereby produces output 5.

REC 8 receives this via multiplexed data line 7 and produces an output 6.

The output 6 is delayed compared to the output 5 corresponding to the delay in the multiplexed data line 7 (FIG. 2a, 5.6).

In DF9, in response to the output of REC8, the clock C
This is read by the rising edge of LK2 and produces a synchronized output (Fig. 2a, 7.8).

If the cable delay in the multiplexed data line 7 is large, the output with less delay, e.g.
Output 1 of 1 is selected by strap 5 and input to DV6.

This produces output 6 via DV6, multiplexed data line 7, and REC8, but output 6 is smaller than output 5 in Figure 2a.
(Figure 2b, 5.6).

In DF9, the clock CLK2 reads the output 6 and produces a synchronized output (Fig. 2b, 7, 8).
.

In this way, in the conventional data transmission synchronization method between devices, it is not only necessary to change the strap connection on the transmitting side depending on the length of the cable between the devices, but also to
There is a drawback that there is a small tolerance for a phase shift between the clock of the second device and the clock of the second device.

The present invention aims to eliminate such drawbacks of the prior art, and its purpose is to eliminate the need for adjustments such as changing strap connections even if the cable length between devices changes, and to eliminate the need for adjustments such as changing the strap connection. The objective is to provide a synchronization scheme that allows some degree of phase shift between the clock of one device and the clock of a second device.

In order to achieve this objective, in the inter-device data transmission synchronization system of the present invention, an inter-device data transmission synchronization system between a first device that transmits time-division multiplexed data and a second device that receives the data is provided. In the data transmission synchronization method, a first clock synchronized with each bit of the data and a second clock synchronized with each plurality of bits of the data are sent from the first device together with the time division multiplexed data. At the same time, a multiphase clock having a period equal to that of the second clock is created based on the first clock and second clock received in the second device, and the time division multiplexed data is multiplexed. By storing each phase of the phase clock as a clock in a register corresponding to each phase, and sequentially selecting the output of each register through a selector controlled by the clock of a second device, received time division multiplexing is performed. It is characterized by synchronizing the converted data with the clock of the second device.

Examples will be described below.

FIG. 3 is a block diagram showing the configuration of an embodiment of the inter-device data transmission synchronization method of the present invention.

In the same figure, 11.12 is a D-type flip-flop (DF), 13, 14.15 is a cable driver (DV
), 16 is a multiplexed data line, 17 is a first clock line,
18 is the second clock line, 1 9 , 20 . 21
is a cable receiver (RFC), 22 is a shift register (SR), 23, 24, 25, 26 are D-type flip-flops (DF), and 27 is a selector (SEL).
), 28 is a counter (CNT), and 29 is a D type flip-flop (DF).

multiplexed data line 16, first clock line 17 and second
With the clock line 18 as an intermediary, the line within the dashed-dotted line on the left side is the first device, and the line between the dashed-dotted line on the right side is the second device, and data is transmitted from the first device to the second device. Indicates when to do so.

4 and 5 are time charts showing signals of various parts in the inter-device data transmission synchronization method of FIG. 3.

In Figures 3 to 5, 1 and 2.3 are respectively D
The output data of V13, 14, 15, 4, 5.6 are the output data of REC19, 20.21, 7, 8,
9.10 is the output of SR22, the first phase and the second phase, respectively.
15 is the clock CLK2 of the second device, 16 is the output of the CNT 28, 17 is the D
The outputs of F29 are shown respectively.

Further, FIG. 4 shows a case where the cable delay is small, and FIG. 5 shows a case where the cable delay is large.

In the first device, the multiplexed data is timed in DF11 by the first device clock CLK1 and then sent out via DV13, and the first clock CLK1 is sent out via DV14 (FIG. 4). and Fig. 5 1, 2).

Further, the first clock CLK, is frequency-divided by 4 in the DF 12 and sent out via the DV 15 as the second clock CLK1' (FIGS. 4 and 5, 3).

Outputs 1, 2.3 are sent to the second device via multiplex line 16, first clock line 17 and second clock line 18, respectively, and outputs 4, 5 via REC 19, 20.21, respectively. 4.5.6 (Figures 4 and 5)
).

In the second device, output 6 is used as an input in SR22, output 5 is used as a clock, and the second clock CLK
, ' are delayed by one cycle of the first clock CLK1 to create a four-phase clock (see Figures 4 and 5, 7,
8,9;10).

DF23 outputs data 4 by first phase clock 7.
Data D.

is stored until it is next rewritten by data D4.

Similarly, the DF 24 stores data D until it is rewritten by the second data D, by the second phase clock 8, and the DF 25 stores data D2 until it is rewritten by the third data D6 by the third phase clock 9. The DF 26 stores the data D3 until it is rewritten by the next data D7 by the fourth phase clock 10.

By repeating this operation, each DF23
, 24, 25, and 26, the bit rate is 1/4 of the bit rate of the output multiplexed data 4, and the data of each cycle is sequentially transmitted as shown in FIGS. 4 and 5. 11.12, 13.14 of FIGS. 4 and 5).

On the other hand, the clock CLK2 of the second device (FIGS. 4 and 5, 15) is applied to the counter 28, producing an output that repeats O to 3 every four cycles (FIGS. 4 and 5, 16). ).

The selector 27 is controlled by this output, and the input terminal X is output.

, X1, X2, and X3, respectively.
, 12, 13, and 14 are sequentially selected to produce an output at output terminal X.

The output X of the SEL 27 is further input to the DF 29, and by reading it using the clock CLK2 as a clock, an output synchronized with the clock CLK2 of the second device is obtained (FIGS. 4 and 5, 17).

As is clear from Figures 4 and 5, regardless of the magnitude of the cable delay, the received data synchronized with the clock of the second device is obtained at the output 17, and the cable delay is automatically absorbed. .

The above explanation deals with the case where the amount of cable delay changes, but even if there is a phase shift between the clock of the first device and the clock of the second device, this can be similarly absorbed to a certain extent. can do.

In addition, when time-divided multiplexed data is sequentially stored in multiple registers and read out using a multiphase clock, the number of registers and the number of phases are determined by the amount of cable delay, the clock of the first device, and the clock of the second device. Needless to say, it can be arbitrarily selected depending on the allowable amount of phase shift between them.

As explained above, according to the inter-device data transmission synchronization method of the present invention, even if the cable length between the devices changes, there is no need to make adjustments such as changing the strap connection, and the first device Since the phase shift between the clock of the second device and the clock of the second device can be tolerated to a certain extent,
Extremely effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional inter-device data transmission synchronization method, FIG. 2 is a time chart showing various signals in the method of FIG. 1, and FIG. A block diagram showing the configuration of one embodiment, and FIGS. 4 and 5 are time charts showing signals of each part in the system of FIG. 3.

Claims (1)

[Claims] 1. In an inter-device data transmission synchronization method between a first device that transmits time-division multiplexed data and a second device that receives the data, the first device transmits the time-division multiplexed data. A first clock synchronized for each bit of the data and a second clock synchronized for each plurality of bits of the data are transmitted together with the data, and the first clock and the second clock synchronized for each bit of the data are transmitted together with the data. A multiphase clock having a period equal to that of the second clock is created based on the clock, and the time-division multiplexed data is stored in registers corresponding to each phase using the valley phase of the multiphase clock as the clock. and the received time division multiplexed data is synchronized with the clock of the second device by sequentially selecting the output of each register via a selector controlled by the clock of the second device. An inter-device data transmission synchronization method.