JPS5746550A - Synchronizing system for data transmission between devices - Google Patents

Synchronizing system for data transmission between devices

Info

Publication number
JPS5746550A
JPS5746550A JP55121897A JP12189780A JPS5746550A JP S5746550 A JPS5746550 A JP S5746550A JP 55121897 A JP55121897 A JP 55121897A JP 12189780 A JP12189780 A JP 12189780A JP S5746550 A JPS5746550 A JP S5746550A
Authority
JP
Japan
Prior art keywords
clock
devices
clock clk1
type
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55121897A
Other languages
Japanese (ja)
Other versions
JPS5849058B2 (en
Inventor
Takashi Nara
Yasutsugu Nagahama
Kenzo Aoki
Hiroshi Miyake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55121897A priority Critical patent/JPS5849058B2/en
Publication of JPS5746550A publication Critical patent/JPS5746550A/en
Publication of JPS5849058B2 publication Critical patent/JPS5849058B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines

Abstract

PURPOSE:To make the change of a strap unnecessary when the cable length between devices is changed, by synchronizing received time division multiplexed data with the clock of a receiving device in case of data transmission between devices which are placed at a comparatively short distance. CONSTITUTION:Multiplexed data is transmitted through a cable driver DV13 after being timed in a D type FF11 by a clock CLK1, and the clock CLK1 and a clock CLK1' divided into four by a D type FF12 are inputted to the second device through DVs 14 and 15, respectively. In a shift register 22, the clock CLK1' is delayed by every one period of the clock CLK1 to generate a four-phase clock. Next, in D type FFs 23, 24, 25 and 26, four signals including data of respective periods successively at the 1/4 bit rate of an output multiple data (4) are generated. These outputs are selected successively by a selector 27 controlled by a clock CLK2 to obtain an output X synchronized with the clock CLK2.
JP55121897A 1980-09-03 1980-09-03 Inter-device data transmission synchronization method Expired JPS5849058B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55121897A JPS5849058B2 (en) 1980-09-03 1980-09-03 Inter-device data transmission synchronization method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55121897A JPS5849058B2 (en) 1980-09-03 1980-09-03 Inter-device data transmission synchronization method

Publications (2)

Publication Number Publication Date
JPS5746550A true JPS5746550A (en) 1982-03-17
JPS5849058B2 JPS5849058B2 (en) 1983-11-01

Family

ID=14822607

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55121897A Expired JPS5849058B2 (en) 1980-09-03 1980-09-03 Inter-device data transmission synchronization method

Country Status (1)

Country Link
JP (1) JPS5849058B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63110838A (en) * 1986-10-29 1988-05-16 Nec Corp Synchronizing signal transfer system

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60107449U (en) * 1983-12-23 1985-07-22 日産ディーゼル工業株式会社 Crank pulley with damper
JPS616641U (en) * 1984-06-18 1986-01-16 株式会社クボタ Engine power take-off device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63110838A (en) * 1986-10-29 1988-05-16 Nec Corp Synchronizing signal transfer system

Also Published As

Publication number Publication date
JPS5849058B2 (en) 1983-11-01

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