JPS57168545A - Controlling system for frame ttransfer phase - Google Patents

Controlling system for frame ttransfer phase

Info

Publication number
JPS57168545A
JPS57168545A JP56053310A JP5331081A JPS57168545A JP S57168545 A JPS57168545 A JP S57168545A JP 56053310 A JP56053310 A JP 56053310A JP 5331081 A JP5331081 A JP 5331081A JP S57168545 A JPS57168545 A JP S57168545A
Authority
JP
Japan
Prior art keywords
frame
phase
transmitting
receiving
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56053310A
Other languages
Japanese (ja)
Other versions
JPS6225305B2 (en
Inventor
Keisuke Hoshino
Yoshiaki Kono
Hajime Kakehi
Hiroshi Takizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56053310A priority Critical patent/JPS57168545A/en
Publication of JPS57168545A publication Critical patent/JPS57168545A/en
Publication of JPS6225305B2 publication Critical patent/JPS6225305B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0647—Synchronisation among TDM nodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0605—Special codes used as synchronising signal
    • H04J3/0608—Detectors therefor, e.g. correlators, state machines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0691—Synchronisation in a TDM node

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To perform the time synchronizing control between the transmitting side and the receiving side without changing the transmitting speed, by varying the transmitting frame length based on a phase controlling command at the transmitting side and varying the receiving frame length based on a command at the receiving side respectively to obtain the frame phase synchronization between the transmitting and receiving sides. CONSTITUTION:An OR circuit 7 of the transmitting side feeds the ordinary count number M+ or -1 and M bit to an N notation counter 9 with the phase advance/ delay command. The counter 9 vaires the control bit of the final frame to vary the frame and to transmit the signal through an OR circuit 15. While at the receiving side, a frame synchronizing circuit 16 estabilishes the frame and multiframe synchronizations, and a control bit decoder 17 decides the advance or delay of the phase of the final frame to feed the phase delay and advance signals LP and SP to an M-2 counter 18, a shift register 19 and an N notation counter 20, respectively. Thus the receiving frame is varied at the receiving side to ensure the frame phase synchronization between the transmitting and receiving sides.
JP56053310A 1981-04-09 1981-04-09 Controlling system for frame ttransfer phase Granted JPS57168545A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56053310A JPS57168545A (en) 1981-04-09 1981-04-09 Controlling system for frame ttransfer phase

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56053310A JPS57168545A (en) 1981-04-09 1981-04-09 Controlling system for frame ttransfer phase

Publications (2)

Publication Number Publication Date
JPS57168545A true JPS57168545A (en) 1982-10-16
JPS6225305B2 JPS6225305B2 (en) 1987-06-02

Family

ID=12939137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56053310A Granted JPS57168545A (en) 1981-04-09 1981-04-09 Controlling system for frame ttransfer phase

Country Status (1)

Country Link
JP (1) JPS57168545A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0642238A2 (en) * 1993-09-08 1995-03-08 Fujitsu Limited Method and apparatus for correcting phase of frames in subsriber loop carrier system
JPH08279805A (en) * 1996-01-19 1996-10-22 Hitachi Ltd Method for recovering timing of receiver side and its device
JP2006345051A (en) * 2005-06-07 2006-12-21 Nec Corp Distribution processing synchronous system utilizing asynchronous clock, master system, and method of controlling clock synchronization

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0642238A2 (en) * 1993-09-08 1995-03-08 Fujitsu Limited Method and apparatus for correcting phase of frames in subsriber loop carrier system
EP0642238A3 (en) * 1993-09-08 1995-09-20 Fujitsu Ltd Method and apparatus for correcting phase of frames in subsriber loop carrier system.
US5528609A (en) * 1993-09-08 1996-06-18 Fujitsu Limited Method and apparatus for correcting phase of frames in subscriber loop carrier system
JPH08279805A (en) * 1996-01-19 1996-10-22 Hitachi Ltd Method for recovering timing of receiver side and its device
JP2006345051A (en) * 2005-06-07 2006-12-21 Nec Corp Distribution processing synchronous system utilizing asynchronous clock, master system, and method of controlling clock synchronization

Also Published As

Publication number Publication date
JPS6225305B2 (en) 1987-06-02

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